Re: MMIO and VERW

[Pawan Gupta]

On Tue, Mar 18, 2025 at 06:37:08PM +0100, Borislav Petkov wrote:
> On Tue, Mar 18, 2025 at 09:56:45AM -0700, Pawan Gupta wrote:
> > On Tue, Mar 18, 2025 at 05:34:51PM +0100, Borislav Petkov wrote:
> > > On Tue, Mar 18, 2025 at 09:25:05AM -0700, Pawan Gupta wrote:
> > > > Rocket Lake, Comet Lake, Ice Lake with tsx=off only require VERW at
> > > > VMENTER. There are other MMIO affected CPUs that are not affected by MDS
> > > > and do not support TSX or disable it by default.
> > > 
> > > So all those CPUs are only affected by MMIO and not affected by neither of
> > > those:
> > > 
> > > TAA, RFDS, MDS
> > 
> > That is correct, they are not affected by MDS, TAA and RFDS.
> > 
> > > Or is that the case only when TSX is not enabled/not present there?
> > 
> > As per the affected CPU table [1], Ice Lake is not affected by TAA even if
> > TSX is enabled.
> 
> That table is insane - I need at least 4 monitors to stare at it properly. :-P

:D Totally agree. A machine readable format is here:
https://github.com/intel/Intel-affected-processor-list/blob/main/Intel_affected_processor_list.csv

> Anyway, so I'm wondering if we special-case those CPUs and have them select
> a special
> 
> MMIO_MITIGATION_VERW_VM
> 
> case and keep them separate from that whole
> CPUs-can-be-affected-by-multiple-vulns and the mitigation for all of them is
> VERW.
> 
> They will enable mmio_stale_data_clear and will be out of the equation.
> 
> Which will make this other logic simpler.

Likely yes, I will give this a shot and see how it compares with the
currrent implementation. Thanks for the suggestion.