Re: [PATCH v2 5/8] coresight: etm3x: Convert raw base pointer to struct coresight access

From: Leo Yan
Date: Wed Mar 19 2025 - 04:31:04 EST

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In reply to: James Clark: "[PATCH v2 5/8] coresight: etm3x: Convert raw base pointer to struct coresight access"
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On Tue, Mar 18, 2025 at 04:21:59PM +0000, James Clark wrote:
> This is so that etm3x can use the new claim tag functions which take a
> csa pointer in a later commit.
>
> Signed-off-by: James Clark <james.clark@xxxxxxxxxx>

LGTM:

Reviewed-by: Leo Yan <leo.yan@xxxxxxx>

> ---
> drivers/hwtracing/coresight/coresight-etm.h | 6 ++---
> drivers/hwtracing/coresight/coresight-etm3x-core.c | 27 +++++++++++-----------
> .../hwtracing/coresight/coresight-etm3x-sysfs.c | 8 +++----
> 3 files changed, 20 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
> index 171f1384f7c0..1d753cca2943 100644
> --- a/drivers/hwtracing/coresight/coresight-etm.h
> +++ b/drivers/hwtracing/coresight/coresight-etm.h
> @@ -229,7 +229,7 @@ struct etm_config {
> * @config: structure holding configuration parameters.
> */
> struct etm_drvdata {
> - void __iomem *base;
> + struct csdev_access csa;
> struct clk *atclk;
> struct coresight_device *csdev;
> spinlock_t spinlock;
> @@ -260,7 +260,7 @@ static inline void etm_writel(struct etm_drvdata *drvdata,
> "invalid CP14 access to ETM reg: %#x", off);
> }
> } else {
> - writel_relaxed(val, drvdata->base + off);
> + writel_relaxed(val, drvdata->csa.base + off);
> }
> }
>
> @@ -274,7 +274,7 @@ static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off)
> "invalid CP14 access to ETM reg: %#x", off);
> }
> } else {
> - val = readl_relaxed(drvdata->base + off);
> + val = readl_relaxed(drvdata->csa.base + off);
> }
>
> return val;
> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> index 8927bfaf3af2..cfd463ac715c 100644
> --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
> @@ -86,9 +86,9 @@ static void etm_set_pwrup(struct etm_drvdata *drvdata)
> {
> u32 etmpdcr;
>
> - etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
> + etmpdcr = readl_relaxed(drvdata->csa.base + ETMPDCR);
> etmpdcr |= ETMPDCR_PWD_UP;
> - writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
> + writel_relaxed(etmpdcr, drvdata->csa.base + ETMPDCR);
> /* Ensure pwrup completes before subsequent cp14 accesses */
> mb();
> isb();
> @@ -101,9 +101,9 @@ static void etm_clr_pwrup(struct etm_drvdata *drvdata)
> /* Ensure pending cp14 accesses complete before clearing pwrup */
> mb();
> isb();
> - etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
> + etmpdcr = readl_relaxed(drvdata->csa.base + ETMPDCR);
> etmpdcr &= ~ETMPDCR_PWD_UP;
> - writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
> + writel_relaxed(etmpdcr, drvdata->csa.base + ETMPDCR);
> }
>
> /**
> @@ -365,7 +365,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> struct etm_config *config = &drvdata->config;
> struct coresight_device *csdev = drvdata->csdev;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(drvdata->csa.base);
>
> rc = coresight_claim_device_unlocked(csdev);
> if (rc)
> @@ -427,7 +427,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata)
> etm_clr_prog(drvdata);
>
> done:
> - CS_LOCK(drvdata->base);
> + CS_LOCK(drvdata->csa.base);
>
> dev_dbg(&drvdata->csdev->dev, "cpu: %d enable smp call done: %d\n",
> drvdata->cpu, rc);
> @@ -549,7 +549,7 @@ static void etm_disable_hw(void *info)
> struct etm_config *config = &drvdata->config;
> struct coresight_device *csdev = drvdata->csdev;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(drvdata->csa.base);
> etm_set_prog(drvdata);
>
> /* Read back sequencer and counters for post trace analysis */
> @@ -561,7 +561,7 @@ static void etm_disable_hw(void *info)
> etm_set_pwrdwn(drvdata);
> coresight_disclaim_device_unlocked(csdev);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(drvdata->csa.base);
>
> dev_dbg(&drvdata->csdev->dev,
> "cpu: %d disable smp call done\n", drvdata->cpu);
> @@ -574,7 +574,7 @@ static void etm_disable_perf(struct coresight_device *csdev)
> if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
> return;
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(drvdata->csa.base);
>
> /* Setting the prog bit disables tracing immediately */
> etm_set_prog(drvdata);
> @@ -586,7 +586,7 @@ static void etm_disable_perf(struct coresight_device *csdev)
> etm_set_pwrdwn(drvdata);
> coresight_disclaim_device_unlocked(csdev);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(drvdata->csa.base);
>
> /*
> * perf will release trace ids when _free_aux()
> @@ -733,7 +733,7 @@ static void etm_init_arch_data(void *info)
> /* Make sure all registers are accessible */
> etm_os_unlock(drvdata);
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(drvdata->csa.base);
>
> /* First dummy read */
> (void)etm_readl(drvdata, ETMPDSR);
> @@ -766,7 +766,7 @@ static void etm_init_arch_data(void *info)
>
> etm_set_pwrdwn(drvdata);
> etm_clr_pwrup(drvdata);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(drvdata->csa.base);
> }
>
> static int __init etm_hp_setup(void)
> @@ -827,8 +827,7 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id)
> if (IS_ERR(base))
> return PTR_ERR(base);
>
> - drvdata->base = base;
> - desc.access = CSDEV_ACCESS_IOMEM(base);
> + desc.access = drvdata->csa = CSDEV_ACCESS_IOMEM(base);
>
> spin_lock_init(&drvdata->spinlock);
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> index b9006451f515..762109307b86 100644
> --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
> @@ -50,11 +50,11 @@ static ssize_t etmsr_show(struct device *dev,
>
> pm_runtime_get_sync(dev->parent);
> spin_lock_irqsave(&drvdata->spinlock, flags);
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(drvdata->csa.base);
>
> val = etm_readl(drvdata, ETMSR);
>
> - CS_LOCK(drvdata->base);
> + CS_LOCK(drvdata->csa.base);
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
> pm_runtime_put(dev->parent);
>
> @@ -949,9 +949,9 @@ static ssize_t seq_curr_state_show(struct device *dev,
> pm_runtime_get_sync(dev->parent);
> spin_lock_irqsave(&drvdata->spinlock, flags);
>
> - CS_UNLOCK(drvdata->base);
> + CS_UNLOCK(drvdata->csa.base);
> val = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
> - CS_LOCK(drvdata->base);
> + CS_LOCK(drvdata->csa.base);
>
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
> pm_runtime_put(dev->parent);
>
> --
> 2.34.1
>

Next message: Leon Romanovsky: "Re: [PATCH v7 00/17] Provide a new two step DMA mapping API"
Previous message: Christian Brauner: "Re: [PATCH] fs: load the ->i_sb pointer once in inode_sb_list_{add,del}"
In reply to: James Clark: "[PATCH v2 5/8] coresight: etm3x: Convert raw base pointer to struct coresight access"
Next in thread: James Clark: "[PATCH v2 7/8] coresight: Remove inlines from static function definitions"
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