Re: [PATCH v4 0/3] drm/tidss: Add OLDI bridge support

[Sverdlin, Alexander]

Thank you for the patches, Aradhya!

On Sun, 2024-11-24 at 20:06 +0530, Aradhya Bhatia wrote:
> Regardless, I'd appreciate it if somebody can test it, and report back if they
> observe any issues.

I've tried to test the patchset with necessary pre-requisites and DT additions
with a single channel LVDS pannel and while I'm not successful yet, I've also noticed
the following warning:

tidss 30200000.dss: vp0: Clock rate 24285714 differs over 5% from requested 37000000

even though later the clock seems to be correctly set up:

$ cat /sys/kernel/debug/clk/clk_summary 

                                 enable  prepare  protect                                duty  hardware                            connection
   clock                          count    count    count        rate   accuracy phase  cycle    enable   consumer                         id
---------------------------------------------------------------------------------------------------------------------------------------------
 clk:186:6                           1       1        0        250000000   0          0     50000      Y   30200000.dss                    fck                      
                                                                                                           deviceless                      no_connection_id         
 clk:186:4                           0       0        0        0           0          0     50000      Y   deviceless                      no_connection_id         
 clk:186:3                           0       0        0        170000000   0          0     50000      Y   deviceless                      no_connection_id         
    clk:186:2                        0       0        0        170000000   0          0     50000      Y      30200000.dss                    vp2                      
                                                                                                              deviceless                      no_connection_id         
 clk:186:0                           1       1        0        259090909   0          0     50000      Y   oldi@0                          serial                   
                                                                                                           deviceless                      no_connection_id         
    clock-divider-oldi               1       1        0        37012987    0          0     50000      Y      30200000.dss                    vp1                      

Looks like "clock-divider-oldi" doesn't propagate clk_set_rate() to the parent,
but the parent is being set later independently?

-- 
Alexander Sverdlin
Siemens AG
www.siemens.com