If a CXL switch is under a CXL root port, The Port GPF Phase timeout
will be updated on the CXL root port when each cxl memory device under
the CXL switch is attaching. It is possible to be updated more than
once. Actually, it is enough to initialize once, other extra
initializations are redundant.
When the first EP attaching, it always triggers its ancestor dports to
locate their own Port GPF DVSEC. The change is that updating Port GPF
Phase timeout on these ancestor dports after ancestor dport locating a
Port GPF DVSEC. It guaranttess that Port GPF Phase timeout updating on a
dport only happens during the first EP attaching.