Re: [PATCH RESEND v5 2/3] clk: canaan: Add clock driver for Canaan K230

[Xukai Wang]

On 2025/3/20 15:09, Troy Mitchell wrote:
> On 2025/3/20 11:25, Xukai Wang wrote:
> ...
>> +struct k230_clk {
>> +	int id;
>> +	struct k230_sysclk *ksc;
>> +	struct clk_hw hw;
>> +};
>> +
>> +#define to_k230_clk(_hw)	container_of(_hw, struct k230_clk, hw)
>> +
>> +/* K230 SYSCLK. */
> Check other places and remove unnecessary comments.
OK, I get it.
>> +
>> +static unsigned long k230_pll_get_rate(struct clk_hw *hw, unsigned long parent_rate)
>> +{
>> +	struct k230_pll *pll = to_k230_pll(hw);
>> +	struct k230_sysclk *ksc = pll->ksc;
>> +	u32 reg;
>> +	u32 r, f, od;
>> +
>> +	reg = readl(pll->bypass);
>> +	if (reg & K230_PLL_BYPASS_ENABLE)
>> +		return parent_rate;
>> +
>> +	reg = readl(pll->lock);
>> +	if (!(reg & (K230_PLL_STATUS_MASK))) { /* unlocked */
> unnecessary comment and wrong position.
I'll modify it.
>> +		dev_err(&ksc->pdev->dev, "%s is unlock.\n", clk_hw_get_name(hw));
>> +		return 0;
>> +	}
>> +
>> +	reg = readl(pll->div);
>> +	r = ((reg >> K230_PLL_R_SHIFT) & K230_PLL_R_MASK) + 1;
>> +	f = ((reg >> K230_PLL_F_SHIFT) & K230_PLL_F_MASK) + 1;
>> +	od = ((reg >> K230_PLL_OD_SHIFT) & K230_PLL_OD_MASK) + 1;
>> +
>> +	return mul_u64_u32_div(parent_rate, f, r * od);
>> +}
>> +
> ...
>
>> +
>> +static int k230_clk_probe(struct platform_device *pdev)
>> +{
>> +	int ret;
>> +	struct k230_sysclk *ksc;
>> +
>> +	ksc = devm_kzalloc(&pdev->dev, sizeof(struct k230_sysclk), GFP_KERNEL);
> you can use `sizeof(*ksc)` instead. same below.
OK, I get it.

And thanks for your review.