Re: [PATCH v1 2/3] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3

[Wenbin Yao (Consultant)]

On 3/21/2025 6:06 AM, Bryan O'Donoghue wrote:
> On 20/03/2025 05:55, Wenbin Yao wrote:
> > From: Qiang Yu <quic_qianyu@xxxxxxxxxxx>
> >
> > Add pcie3port node to represent the PCIe bridge of PCIe3 so that PCI 
> > slot
> > voltage rails can be described under this node in the board's dts.
> >
> > Signed-off-by: Qiang Yu <quic_qianyu@xxxxxxxxxxx>
> > Signed-off-by: Wenbin Yao <quic_wenbyao@xxxxxxxxxxx>
> > ---
> >   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi 
> > b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > index 46b79fce9..32e8d400a 100644
> > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > @@ -3287,6 +3287,16 @@ opp-128000000 {
> >                       opp-peak-kBps = <15753000 1>;
> >                   };
> >               };
> > +            pcie3port: pcie@0 { 
>
> Missing newline, please check your dtb checks.

Will fix in the next version.

> > +                device_type = "pci";
> > +                compatible = "pciclass,0604";
> > +                reg = <0x0 0x0 0x0 0x0 0x0>;
> > +                bus-range = <0x01 0xff>;
> > +
> > +                #address-cells = <3>;
> > +                #size-cells = <2>;
> > +                ranges;
> > +            };
> >           };
>
> Why is pice3port the only port to be enabled ?
>
> What about the other ports ?

Only PCIe3 requires PCI slot power driver to power on its slots, other
ports don‘t need it.

> >           pcie3_phy: phy@1be0000 {
> > --
> > 2.34.1
>
> ---
> bod

--
With best wishes
Wenbin