[PATCH 0/3] RISC-V KVM selftests improvements

From: Atish Patra
Date: Mon Mar 24 2025 - 20:40:50 EST


This series improves the following tests.
1. Get-reg-list : Adds vector support
2. SBI PMU test : Distinguish between different types of illegal exception

The first patch is just helper patch that adds stval support during
exception handling.

Signed-off-by: Atish Patra <atishp@xxxxxxxxxxxx>
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Atish Patra (3):
KVM: riscv: selftests: Add stval to exception handling
KVM: riscv: selftests: Decode stval to identify exact exception type
KVM: riscv: selftests: Add vector extension tests

.../selftests/kvm/include/riscv/processor.h | 1 +
tools/testing/selftests/kvm/lib/riscv/handlers.S | 2 +
tools/testing/selftests/kvm/riscv/get-reg-list.c | 111 ++++++++++++++++++++-
tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 32 ++++++
4 files changed, 145 insertions(+), 1 deletion(-)
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base-commit: b3f263a98d30fe2e33eefea297598c590ee3560e
change-id: 20250324-kvm_selftest_improve-9bedb9f0a6d3
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Regards,
Atish patra