Re: [PATCH v2 2/6] phy: qcom-qmp-ufs: Add PHY Configuration support for sm8750
From: Nitin Rawat
Date: Tue Mar 25 2025 - 03:38:31 EST
On 3/25/2025 1:04 PM, neil.armstrong@xxxxxxxxxx wrote:
Hi,
On 25/03/2025 04:12, Nitin Rawat wrote:
On 3/24/2025 11:40 PM, Neil Armstrong wrote:
Hi,
On 10/03/2025 22:12, Melody Olvera wrote:
From: Nitin Rawat <quic_nitirawa@xxxxxxxxxxx>
Add SM8750 specific register layout and table configs. The serdes
TX RX register offset has changed for SM8750 and hence keep UFS
specific serdes offsets in a dedicated header file.
Reviewed-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
Co-developed-by: Manish Pandey <quic_mapa@xxxxxxxxxxx>
Signed-off-by: Manish Pandey <quic_mapa@xxxxxxxxxxx>
Signed-off-by: Nitin Rawat <quic_nitirawa@xxxxxxxxxxx>
---
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 7 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v7.h | 67 ++++++++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 180 +++++++++
++ +++++++++-
3 files changed, 246 insertions(+), 8 deletions(-)
<snip>
This change breaks UFS on the SM8550-HDK:
[ 7.418161] qcom-qmp-ufs-phy 1d80000.phy: phy initialization
timed-out
[ 7.427021] phy phy-1d80000.phy.0: phy poweron failed --> -110
[ 7.493514] ufshcd-qcom 1d84000.ufshc: Enabling the controller failed
...
Hi Neil,
Thanks for testing and reporting.
I did tested this patch on SM8750 MTP, SM8750 QRD, SM8650 MTP, SM8550
MTP and SM8850 QRD all of these have rate B and hence no issue.
Unfortunately only SM8550 HDK platform which UFS4.0 and RateA couldn't
get tested. As we know SM8550 with gear 5 only support rate A.
I was applying rate B setting without checking for mode type. Since
SM8550 is only platform which support only rate A with UFS4.0 . Hence
this could be the issue.
Meanwhile can you help test at your end with below change and let me
if it resolves for you. I will also try at my end to test as well.
=============================================================================
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/
qualcomm/phy-qcom-qmp-ufs.c
index 45b3b792696e..b33e2e2b5014 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -1754,7 +1754,8 @@ static void qmp_ufs_init_registers(struct
qmp_ufs *qmp, const struct qmp_phy_cfg
qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]);
}
- qmp_ufs_init_all(qmp, &cfg->tbls_hs_b);
+ if (qmp->mode == PHY_MODE_UFS_HS_B)
+ qmp_ufs_init_all(qmp, &cfg->tbls_hs_b);
}
=================================================================================
With this change the UFS works again.
Thanks Neil for quick revert. I'll raise the official change.
Regards,
nitin
Thanks,
Neil
Thanks,
Nitin
GIT bisect points to:
b02cc9a176793b207e959701af1ec26222093b05 is the first bad commit
Author: Nitin Rawat <quic_nitirawa@xxxxxxxxxxx>
Date: Mon Mar 10 14:12:30 2025 -0700
phy: qcom-qmp-ufs: Add PHY Configuration support for sm8750
bisect log:
git bisect start 'ff7f9b199e3f' 'v6.14-rc1'
git bisect good 36c18c562846300d4e59f1a65008800b787f4fe4
git bisect good 85cf0293c3a75726e7bc54d3efdc5dc783debc07
git bisect good b2cd73e18cec75f917d14b9188f82a2fdef64ebe
git bisect bad b247639d33ad16ea76797268fd0eef08d8027dfd
git bisect good 9b3f2dfdad1cc0ab90a0fa371c8cbee08b2446e3
git bisect bad 8dc30c3e4cf8c4e370cf08bd09eb87b0deccd3de
git bisect bad 100aeb03a437f30300894091627e4406605ee3cb
git bisect bad b2a1a2ae7818c9d8da12bf7b1983c8b9f5fb712b
git bisect good 8f831f272b4c89aa13b45bd010c2c18ad97a3f1b
git bisect good e45cc62c23428eefbae18a9b4d88d10749741bdd
git bisect bad ebf198f17b5ac967db6256f4083bbcbdcc2a3100
git bisect good 12185bc38f7667b1d895b2165a8a47335a4cf31b
git bisect bad e46e59b77a9e6f322ef1ad08a8874211f389cf47
git bisect bad b02cc9a176793b207e959701af1ec26222093b05
CI run: https://git.codelinaro.org/linaro/qcomlt/ci/staging/cdba-
tester/-/jobs/229880#L1281
#regzbot introduced: b02cc9a17679
Neil