Re: [PATCH 1/4] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC

[Krzysztof Kozlowski]

On Tue, Mar 25, 2025 at 12:59:49AM +0100, Konrad Dybcio wrote:
> On 3/25/25 12:57 AM, Konrad Dybcio wrote:
> > On 3/21/25 1:49 PM, Luo Jie wrote:
> >> The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference
> >> input clock. The output clocks are the same as IPQ9574 SoC, except
> >> for the clock rate of output clocks to PPE and NSS.
> >>
> >> Also, add macros for clock rates that are applicable specifically
> >> only for IPQ5424.
> >>
> >> Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx>
> >> ---
> >>  .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml        |  1 +
> >>  include/dt-bindings/clock/qcom,ipq-cmn-pll.h                   | 10 +++++++++-
> >>  2 files changed, 10 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> >> index f869b3739be8..bbaf896ae908 100644
> >> --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> >> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
> >> @@ -25,6 +25,7 @@ properties:
> >>    compatible:
> >>      enum:
> >>        - qcom,ipq9574-cmn-pll
> >> +      - qcom,ipq5424-cmn-pll
> >>  
> >>    reg:
> >>      maxItems: 1
> >> diff --git a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
> >> index 936e92b3b62c..e30d57001c38 100644
> >> --- a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
> >> +++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
> >> @@ -1,6 +1,6 @@
> >>  /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> >>  /*
> >> - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> >> + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
> >>   */
> >>  
> >>  #ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
> >> @@ -19,4 +19,12 @@
> >>  #define ETH1_50MHZ_CLK			7
> >>  #define ETH2_50MHZ_CLK			8
> >>  #define ETH_25MHZ_CLK			9
> >> +
> >> +/*
> >> + * The CMN PLL output clock rates that are specifically applicable for IPQ5424
> >> + * SoC. For IPQ5424, the other output clocks and their rates are same as IPQ9574.
> >> + */
> >> +#define NSS_300MHZ_CLK			4
> >> +#define PPE_375MHZ_CLK			5
> > 
> > Not a huge fan of this, such differences are only relevant to the driver
> > part in my view - bindings only let a consumer reference a specific piece
> > of hardware
> 
> Oh I the bindings are stepping into the frequency department already,
> hmm.. Then I suppose it's fine if the dt-bindings maintainers don't have any
> concerns


Nooooo, it was said these are output clocks, not rates. If these are
rates, then NAK.

Best regards,
Krzysztof