Re: [PATCH v1 0/5] Add snps,dis_u3_susphy_quirk for some QC targets

From: Krishna Kurapati
Date: Wed Mar 26 2025 - 01:23:12 EST




On 3/26/2025 5:51 AM, Dmitry Baryshkov wrote:
On Tue, Mar 25, 2025 at 08:31:55PM +0530, Prashanth K wrote:


On 25-03-25 08:11 pm, Konrad Dybcio wrote:
On 3/25/25 1:30 PM, Prashanth K wrote:
During device mode initialization on certain QC targets, before the
runstop bit is set, sometimes it's observed that the GEVNTADR{LO/HI}
register write fails. As a result, GEVTADDR registers are still 0x0.
Upon setting runstop bit, DWC3 controller attempts to write the new
events to address 0x0, causing an SMMU fault and system crash. More
info about the crash at [1].

This was initially observed on SM8450 and later reported on few
other targets as well. As suggested by Qualcomm HW team, clearing
the GUSB3PIPECTL.SUSPHY bit resolves the issue by preventing register
write failures. Address this by setting the snps,dis_u3_susphy_quirk
to keep the GUSB3PIPECTL.SUSPHY bit cleared. This change was tested
on multiple targets (SM8350, SM8450 QCS615 etc.) for over an year
and hasn't exhibited any side effects.

[1]: https://lore.kernel.org/all/fa94cbc9-e637-ba9b-8ec8-67c6955eca98@xxxxxxxxxxx/

Prashanth K (3):
arm64: dts: qcom: sm8150: Add snps,dis_u3_susphy_quirk
arm64: dts: qcom: sm8350: Add snps,dis_u3_susphy_quirk
arm64: dts: qcom: sm8450: Add snps,dis_u3_susphy_quirk

It is hard to belive that this quirk is to be set for SM8150, SM8350,
SM8450, but not SM8250.


At the moment we wanted to add this quirk for targets where issue has shown up either internal to QC or at customer's end. But the issue didn't come up on SM8250/ SM8550/ SM8650 so far either from customer end or ours. Would like to update for other targets on need basis.

Regards,
Krishna,


Pratham Pratap (2):
arm64: dts: qcom: qcs615: Add snps,dis_u3_susphy_quirk
arm64: dts: qcom: qdu1000: Add snps,dis_u3_susphy_quirk

Are there more targets affected, from the list of the ones currently
supported upstream?

Konrad

My initial plan was to add it for all the QC platforms, but wasn't
confident enough about it. Because we have seen the issue only on these
targets and hence tested only on these.

Regards,
Prashanth K