Re: [PATCH v2 5/6] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe
From: Frank Li
Date: Wed Mar 26 2025 - 10:45:26 EST
On Wed, Mar 26, 2025 at 03:59:14PM +0800, Richard Zhu wrote:
> Add PLL clock lock check for i.MX95 PCIe.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> ---
Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> drivers/pci/controller/dwc/pci-imx6.c | 28 +++++++++++++++++++++++++--
> 1 file changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 42683d6be9f2..1c8834fbcfd5 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -45,6 +45,9 @@
> #define IMX95_PCIE_PHY_GEN_CTRL 0x0
> #define IMX95_PCIE_REF_USE_PAD BIT(17)
>
> +#define IMX95_PCIE_PHY_MPLLA_CTRL 0x10
> +#define IMX95_PCIE_PHY_MPLL_STATE BIT(30)
> +
> #define IMX95_PCIE_SS_RW_REG_0 0xf0
> #define IMX95_PCIE_REF_CLKEN BIT(23)
> #define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9)
> @@ -478,6 +481,23 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
> dev_err(dev, "PCIe PLL lock timeout\n");
> }
>
> +static int imx95_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
> +{
> + u32 val;
> + struct device *dev = imx_pcie->pci->dev;
> +
> + if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr,
> + IMX95_PCIE_PHY_MPLLA_CTRL, val,
> + val & IMX95_PCIE_PHY_MPLL_STATE,
> + PHY_PLL_LOCK_WAIT_USLEEP_MAX,
> + PHY_PLL_LOCK_WAIT_TIMEOUT)) {
> + dev_err(dev, "PCIe PLL lock timeout\n");
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> +
> static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie)
> {
> unsigned long phy_rate = 0;
> @@ -821,6 +841,8 @@ static int imx95_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert)
> regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_RST_CTRL,
> IMX95_PCIE_COLD_RST);
> udelay(10);
> + } else {
> + return imx95_pcie_wait_for_phy_pll_lock(imx_pcie);
> }
>
> return 0;
> @@ -840,11 +862,13 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
>
> static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
> {
> + int ret = 0;
> +
> reset_control_deassert(imx_pcie->pciephy_reset);
> reset_control_deassert(imx_pcie->apps_reset);
>
> if (imx_pcie->drvdata->core_reset)
> - imx_pcie->drvdata->core_reset(imx_pcie, false);
> + ret = imx_pcie->drvdata->core_reset(imx_pcie, false);
>
> /* Some boards don't have PCIe reset GPIO. */
> if (imx_pcie->reset_gpiod) {
> @@ -854,7 +878,7 @@ static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
> msleep(100);
> }
>
> - return 0;
> + return ret;
> }
>
> static int imx_pcie_wait_for_speed_change(struct imx_pcie *imx_pcie)
> --
> 2.37.1
>