Re: [PATCH 0/7] Enhance the PCIe controller driver

[Hans Zhang]

Hi Manikandan,

You should update your patch to V2, not no version at all.

Best regards,
Hans

On 2025/3/27 18:59, Manikandan Karunakaran Pillai wrote:
> EXTERNAL EMAIL
>
> Enhances the exiting Cadence PCIe controller drivers to support second
> generation PCIe controller also referred as HPA(High Performance
> Architecture) controllers.
>
> The patch set enhances the Cadence PCIe driver for the new high
> performance architecture changes. The "compatible" property in DTS
> is added with  more strings to support the new platform architecture
> and the register maps that change with it. The driver read register
> and write register functions take the updated offset stored from the
> platform driver to access the registers. The driver now supports
> the legacy and HPA architecture, with the legacy code being changed
> minimal. The TI SoC continues to be supported with the changes
> incorporated. The changes are also in tune with how multiple platforms
> are supported in related drivers.
>
> Patch 1/7 - DTS related changes for property "compatible"
> Patch 2/7 - Updates the header file with relevant register offsets and
>              bit definitions
> Patch 3/7 - Platform related code changes
> Patch 4/7 - PCIe EP related code changes
> Patch 5/7 - Header file is updated with register offsets and updated
>              read and write register functions
> Patch 6/7 - Support for multiple arch by using registered callbacks
> Patch 7/7 - TIJ72X board is updated to use the new approach
>
> Comments from the earlier patch submission on the same enhancements are
> taken into consideration. The previous submitted patch links is
> https://lore.kernel.org/lkml/CH2PPF4D26F8E1C205166209F012D4F3A81A2A42@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx/
>
> The scripts/checkpatch.pl has been run on the patches with and without
> --strict. With the --strict option, 4 checks are generated on 1 patch
> (patch 0002 of the series), which can be ignored. There are no code
> fixes required for these checks. The rest of the 'scripts/checkpatch.pl'
> is clean.
>
> The changes are tested on TI platforms. The legacy controller changes are
> tested on an TI J7200 EVM and HPA changes are planned for on an FPGA
> platform available within Cadence.
>
> Manikandan K Pillai (7):
>    dt-bindings: pci: cadence: Extend compatible for new platform
>      configurations
>    PCI: cadence: Add header support for PCIe next generation controllers
>    PCI: cadence: Add platform related architecture and register
>      information
>    PCI: cadence: Add support for PCIe Endpoint HPA controllers
>    PCI: cadence: Update the PCIe controller register address offsets
>    PCI: cadence: Add callback functions for Root Port and EP controller
>    PCI: cadence: Update support for TI J721e boards
>
>   .../bindings/pci/cdns,cdns-pcie-ep.yaml       |  12 +-
>   .../bindings/pci/cdns,cdns-pcie-host.yaml     | 119 +++++-
>   drivers/pci/controller/cadence/pci-j721e.c    |   8 +
>   .../pci/controller/cadence/pcie-cadence-ep.c  | 184 +++++++--
>   .../controller/cadence/pcie-cadence-host.c    | 264 ++++++++++--
>   .../controller/cadence/pcie-cadence-plat.c    | 145 +++++++
>   drivers/pci/controller/cadence/pcie-cadence.c | 217 +++++++++-
>   drivers/pci/controller/cadence/pcie-cadence.h | 380 +++++++++++++++++-
>   8 files changed, 1259 insertions(+), 70 deletions(-)
>
> --
> 2.27.0