[PATCH v5 07/21] dt-bindings: riscv: add Smcntrpmf ISA extension description

From: Atish Patra
Date: Thu Mar 27 2025 - 15:38:24 EST


Add the description for Smcntrpmf ISA extension

Acked-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
Signed-off-by: Atish Patra <atishp@xxxxxxxxxxxx>
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 0520a9d8b1cd..c2025949295f 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -136,6 +136,12 @@ properties:
mechanism in M-mode as ratified in the 20240326 version of the
privileged ISA specification.

+ - const: smcntrpmf
+ description: |
+ The standard Smcntrpmf supervisor-level extension for the machine mode
+ to enable privilege mode filtering for cycle and instret counters as
+ ratified in the 20240326 version of the privileged ISA specification.
+
- const: smmpm
description: |
The standard Smmpm extension for M-mode pointer masking as

--
2.43.0