Re: [PATCH v8 2/4] PCI: of: Add of_pci_get_equalization_presets() API

[Krishna Chaitanya Chundru]

On 3/28/2025 10:09 AM, Manivannan Sadhasivam wrote:
> On Sun, Mar 16, 2025 at 09:39:02AM +0530, Krishna Chaitanya Chundru wrote:
> > PCIe equalization presets are predefined settings used to optimize
> > signal integrity by compensating for signal loss and distortion in
> > high-speed data transmission.
> >
> > As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates
> > of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to
> > configure lane equalization presets for each lane to enhance the PCIe
> > link reliability. Each preset value represents a different combination
> > of pre-shoot and de-emphasis values. For each data rate, different
> > registers are defined: for 8.0 GT/s, registers are defined in section
> > 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has
> > an extra receiver preset hint, requiring 16 bits per lane, while the
> > remaining data rates use 8 bits per lane.
> >
> > Based on the number of lanes and the supported data rate,
> > of_pci_get_equalization_presets() reads the device tree property and
> > stores in the presets structure.
> >
> > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
> > ---
> >   drivers/pci/of.c  | 44 ++++++++++++++++++++++++++++++++++++++++++++
> >   drivers/pci/pci.h | 32 +++++++++++++++++++++++++++++++-
> >   2 files changed, 75 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/of.c b/drivers/pci/of.c
> > index 7a806f5c0d20..18691483e108 100644
> > --- a/drivers/pci/of.c
> > +++ b/drivers/pci/of.c
> > @@ -851,3 +851,47 @@ u32 of_pci_get_slot_power_limit(struct device_node *node,
> >   	return slot_power_limit_mw;
> >   }
> >   EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit);
> > +
> > +/**
> > + * of_pci_get_equalization_presets - Parses the "eq-presets-Ngts" property.
> > + *
> > + * @dev: Device containing the properties.
> > + * @presets: Pointer to store the parsed data.
> > + * @num_lanes: Maximum number of lanes supported.
> > + *
> > + * If the property is present, read and store the data in the @presets structure.
> > + * Else, assign a default value of PCI_EQ_RESV.
> > + *
> > + * Return: 0 if the property is not available or successfully parsed else
> > + * errno otherwise.
> > + */
> > +int of_pci_get_equalization_presets(struct device *dev,
> > +				    struct pci_eq_presets *presets,
> > +				    int num_lanes)
> > +{
> > +	char name[20];
> > +	int ret;
> > +
> > +	presets->eq_presets_8gts[0] = PCI_EQ_RESV;
> > +	ret = of_property_read_u16_array(dev->of_node, "eq-presets-8gts",
> > +					 presets->eq_presets_8gts, num_lanes);
> > +	if (ret && ret != -EINVAL) {
> > +		dev_err(dev, "Error reading eq-presets-8gts :%d\n", ret);
>
> 'Error reading eq-presets-8gts: %d'
>
> > +		return ret;
> > +	}
> > +
> > +	for (int i = 0; i < EQ_PRESET_TYPE_MAX - 1; i++) {
> > +		presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV;
> > +		snprintf(name, sizeof(name), "eq-presets-%dgts", 8 << (i + 1));
> > +		ret = of_property_read_u8_array(dev->of_node, name,
> > +						presets->eq_presets_Ngts[i],
> > +						num_lanes);
> > +		if (ret && ret != -EINVAL) {
> > +			dev_err(dev, "Error reading %s :%d\n", name, ret);
>
> 'Error reading %s: %d'
>
> > +			return ret;
> > +		}
> > +	}
> > +
> > +	return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(of_pci_get_equalization_presets);
> > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> > index 01e51db8d285..78c9cc0ad8fa 100644
> > --- a/drivers/pci/pci.h
> > +++ b/drivers/pci/pci.h
> > @@ -9,6 +9,8 @@ struct pcie_tlp_log;
> >   /* Number of possible devfns: 0.0 to 1f.7 inclusive */
> >   #define MAX_NR_DEVFNS 256
> >   
> > +#define MAX_NR_LANES 16
>
> Why did you limit to 16?
As per PCIe spec we support maximum of 16 lanes only right

- Krishna Chaitanya.
> - Mani