[PATCH v5 04/35] perf vendor events: Update bonnell events

From: Ian Rogers
Date: Fri Mar 28 2025 - 13:51:04 EST


Move DISPATCH_BLOCKED.ANY to the pipeline topic.

Signed-off-by: Ian Rogers <irogers@xxxxxxxxxx>
---
tools/perf/pmu-events/arch/x86/bonnell/other.json | 8 --------
tools/perf/pmu-events/arch/x86/bonnell/pipeline.json | 8 ++++++++
2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/bonnell/other.json b/tools/perf/pmu-events/arch/x86/bonnell/other.json
index 3a55c101fbf7..6e6f64b96834 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/other.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/other.json
@@ -323,14 +323,6 @@
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
- {
- "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
- "Counter": "0,1",
- "EventCode": "0x9",
- "EventName": "DISPATCH_BLOCKED.ANY",
- "SampleAfterValue": "200000",
- "UMask": "0x20"
- },
{
"BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
"Counter": "0,1",
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
index 9ff032ab11e2..48d3d053a369 100644
--- a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
@@ -211,6 +211,14 @@
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
+ "Counter": "0,1",
+ "EventCode": "0x9",
+ "EventName": "DISPATCH_BLOCKED.ANY",
+ "SampleAfterValue": "200000",
+ "UMask": "0x20"
+ },
{
"BriefDescription": "Divide operations retired",
"Counter": "0,1",
--
2.49.0.472.ge94155a9ec-goog