RE: [PATCH 0/6] clk: renesas: rzv2h: Add clock and reset entries for USB2 and GBETH

[Biju Das]

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
> Sent: 31 March 2025 11:21
> Subject: Re: [PATCH 0/6] clk: renesas: rzv2h: Add clock and reset entries for USB2 and GBETH
> 
> Hi Biju,
> 
> On Mon, 31 Mar 2025 at 12:13, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> > > From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> On Fri, 28 Mar 2025
> > > at 21:01, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > > > Note, these patch apply on top of the following patch series:
> > > > https://lore.kernel.org/all/20250228202655.491035-1-prabhakar.maha
> > > > dev-
> > > > lad.rj@xxxxxxxxxxxxxx/
> > >
> > > That patch series was ultimately ignored because it was not clear
> > > how it related to other similar patches for the same driver.  So
> > > please coordinate and resend, based on renesas-clk-for-v6.16, or
> > > even better,
> > > v6.15-rc1 next week.
> >
> > DEF_CSDIV macro for clk divider with custom code as it requires RMW operation.
> >
> > and
> >
> > DEF_SDIV macro for clk divider with generic API.
> >
> > So, you mean use DEF_CSDIV macro for clk divider with generic API ??
> 
> No, I mean you and Prabhakar should coordinate, and resend any series which you still want to see
> applied.

Thanks, it is clear now.

Cheers,
Biju