Re: [PATCH 2/3] irqchip/gic: Use 0x10000 offset to access GICC_DIR on STM32MP2

[Christian Bruel]

Hello Thomas,

thanks for your comments.
After Marc's suggestion we found a better solution. So dropping this 
patch set.

Christian

On 4/3/25 17:43, Thomas Gleixner wrote:
> On Thu, Apr 03 2025 at 14:28, Christian Bruel wrote:
>
> > When GIC_4KNOT64K bit in the GIC configuration register is
> > 0 (64KB), address block is modified in such a way than only the
>
> s/than/that/
>
> > first 4KB of the GIC cpu interface are accessible with default
> > offsets.
> > With this bit mapping GICC_DIR register is accessible at
>
> What's 'this bit mapping' ? This sentence does not parse.
>
> > offset 0x10000 instead of 0x1000, thus remap accordingly
>
> ...
>
> > +/*
> > + * 8kB GICC range is not accessible with the default 4kB translation
> > + * granule. 0x1000 offset is accessible at 64kB translation.
> > + */
>
> I have a hard time to map this comment to the change log, which suggests
> to me that this is the other way round.
>
> > +static bool gic_8kbaccess(void *data)
> > +{
> > +	struct gic_chip_data *gic = data;
> > +	void __iomem *alt;
> > +
> > +	if (!is_hyp_mode_available())
> > +		return false;
> > +
> > +	alt = ioremap(gic->cpu_phys_base, GIC_STM32MP2_CPU_DEACTIVATE + 4);
> > +	if (!alt) {
> > +		pr_err("Unable to remap GICC_DIR register\n");
> > +		return false;
>
> That's a hack because in case that the remap fails, this leaves the
> thing enabled, but disfunctional.
>
> Thanks,
>
>          tglx