[PATCH 0/9] add Voyager board support

From: Ben Zong-You Xie
Date: Mon Apr 07 2025 - 07:13:16 EST


The Voyager is a 9.6” x 9.6” Micro ATX form factor development board including
Andes QiLai SoC. This patch series adds minimal device tree files for the QiLai
SoC and the Voyager board [1].

Now only support basic uart drivers to boot up into a basic console. Other
features will be added later.

[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/

Ben Zong-You Xie (9):
riscv: add Andes SoC family Kconfig support
dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
dt-bindings: interrupt-controller: add Andes QiLai PLIC
dt-bindings: interrupt-controller: add Andes machine-level software
interrupt controller
dt-bindings: timer: add Andes machine timer
dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes
L2 cache
riscv: dts: andes: add QiLai SoC device tree
riscv: dts: andes: add Voyager board device tree
riscv: defconfig: enable Andes SoC

.../cache/andestech,ax45mp-cache.yaml | 2 +-
.../andestech,plicsw.yaml | 48 +++++
.../sifive,plic-1.0.0.yaml | 1 +
.../devicetree/bindings/riscv/andes.yaml | 25 +++
.../bindings/timer/andestech,plmt0.yaml | 42 ++++
MAINTAINERS | 8 +
arch/riscv/Kconfig.errata | 2 +-
arch/riscv/Kconfig.socs | 9 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/andes/Makefile | 2 +
arch/riscv/boot/dts/andes/qilai-voyager.dts | 19 ++
arch/riscv/boot/dts/andes/qilai.dtsi | 194 ++++++++++++++++++
arch/riscv/configs/defconfig | 1 +
13 files changed, 352 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml
create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
create mode 100644 arch/riscv/boot/dts/andes/Makefile
create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts
create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi

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2.34.1