Re: [PATCH v6 11/11] arm64: dts: ti: k3-am64: Reserve timers used by MCU FW

From: Andrew Davis
Date: Mon Apr 07 2025 - 08:37:58 EST


On 4/4/25 7:15 PM, Judith Mendez wrote:
From: Hari Nagalla <hnagalla@xxxxxx>

AM64x device has 4 R5F cores in the main domain. TI MCU firmware uses
main domain timers as tick timers in these firmwares. Hence keep them
as reserved in the Linux device tree.

Signed-off-by: Hari Nagalla <hnagalla@xxxxxx>
Signed-off-by: Judith Mendez <jm@xxxxxx>
---
arch/arm64/boot/dts/ti/k3-am642-evm.dts | 17 +++++++++++++++++
arch/arm64/boot/dts/ti/k3-am642-sk.dts | 17 +++++++++++++++++
2 files changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index f8ec40523254b..68bd6b806f8f0 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -796,6 +796,23 @@ &mcu_m4fss {
status = "okay";
};
+/* main_timers 8-11 are used by TI MCU FW */

Can you make this comment per-core and explain which core
each timer is reserved for? Makes it easier on me in Zephyr
to point out why we use the timers that we do, something
like:

/* main_timer8 is reserved for mcu_r5fss0_core0 */

Andrew

+&main_timer8 {
+ status = "reserved";
+};
+
+&main_timer9 {
+ status = "reserved";
+};
+
+&main_timer10 {
+ status = "reserved";
+};
+
+&main_timer11 {
+ status = "reserved";
+};
+
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
};
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 33e421ec18abb..07fbdf2400d23 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -710,6 +710,23 @@ &mcu_m4fss {
status = "okay";
};
+/* main_timers 8-11 are used by TI MCU FW */
+&main_timer8 {
+ status = "reserved";
+};
+
+&main_timer9 {
+ status = "reserved";
+};
+
+&main_timer10 {
+ status = "reserved";
+};
+
+&main_timer11 {
+ status = "reserved";
+};
+
&ecap0 {
status = "okay";
/* PWM is available on Pin 1 of header J3 */