Re: [PATCH] PCI: dwc: Set PORT_LOGIC_LINK_WIDTH to one lane

[Manivannan Sadhasivam]

On Thu, Dec 12, 2024 at 04:19:12PM +0800, Wenbin Yao (Consultant) wrote:
> PORT_LOGIC_LINK_WIDTH field of the PCIE_LINK_WIDTH_SPEED_CONTROL register
> indicates the number of lanes to check for exit from Electrical Idle in
> Polling.Active and L2.Idle. It is used to limit the effective link width to
> ignore broken or unused lanes that detect a receiver to prevent one or more
> bad Receivers or Transmitters from holding up a valid Link from being
> configured.
> 
> In a PCIe link that support muiltiple lanes, setting PORT_LOGIC_LINK_WIDTH
> to 1 will not affect the link width that is actually intended to be used.

Where in the spec it is defined?

> But setting it to a value other than 1 will lead to link training fail if
> one or more lanes are broken.
> 

Which means the link partner is not able to downsize the link during LTSSM?

> Hence, always set PORT_LOGIC_LINK_WIDTH to 1 no matter how many lanes the
> port actually supports to make linking up more robust. Link can still be
> established with one lane at least if other lanes are broken.
> 

This looks like a specific endpoint/controller issue to me. Where exactly did
you see the issue?

- Mani

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