Re: [PATCH 0/2] J722S: Disable WIZ0 and WIZ1 in SoC file

[Siddharth Vadapalli]

On Tue, Apr 08, 2025 at 11:36:34AM +0530, Siddharth Vadapalli wrote:
> Hello,
> 
> This series disables the "serdes_wiz0" and "serdes_wiz1" device-tree
> nodes in the J722S SoC file and enables them in the board files where
> they are required along with "serdes0" and "serdes1". There are two
> reasons behind this change:
> 1. To follow the existing convention of disabling nodes in the SoC file
>    and enabling them in the board file as required.
> 2. To address situations where a board file hasn't explicitly disabled
>    "serdes_wiz0" and "serdes_wiz1" (example: am67a-beagley-ai.dts)
>    as a result of which booting the board displays the following errors:
>      wiz bus@f0000:phy@f000000: probe with driver wiz failed with error -12
>      ...
>      wiz bus@f0000:phy@f010000: probe with driver wiz failed with error -12

Since this series fixes the above errors on Beagley-AI, I will include
the "Fixes" tag in the commit message of the respective patches in this
series and post the v2 series.

Regards,
Siddharth.