Re: [PATCH 7/9] riscv: dts: andes: add QiLai SoC device tree

[Conor Dooley]

On Mon, Apr 07, 2025 at 06:49:35PM +0800, Ben Zong-You Xie wrote:
> Introduce the initial device tree support for the Andes QiLai SoC.
> 
> For further information, you can refer to [1].
> 
> [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
> 
> Signed-off-by: Ben Zong-You Xie <ben717@xxxxxxxxxxxxx>
> ---
>  MAINTAINERS                          |   1 +
>  arch/riscv/boot/dts/andes/qilai.dtsi | 194 +++++++++++++++++++++++++++
>  2 files changed, 195 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index d1e1b98dfe7b..b974e83c9f10 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -20731,6 +20731,7 @@ S:	Maintained
>  F:	Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
>  F:	Documentation/devicetree/bindings/riscv/andes.yaml
>  F:	Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
> +F:	arch/riscv/boot/dts/andes/

New platform, but your maintainers entry contains no git tree. Who are
you expecting to apply patches and send PRs to the soc maintainers for
this platform? Hint: I really hope it is you.

If it is you, please look at the soc platform maintainers documentation
entry:
https://docs.kernel.org/process/maintainer-soc.html

Cheers,
Conor.

Attachment: signature.asc
Description: PGP signature