Re: [PATCH] x86/cpufeatures: Define X86_FEATURE_PREFETCHI (AMD)

[Borislav Petkov]

On Tue, Apr 08, 2025 at 05:57:09PM -0500, Babu Moger wrote:
> The latest AMD platform has introduced a new instruction called PREFETCHI.
> This instruction loads a cache line from a specified memory address into
> the indicated data or instruction cache level, based on locality reference
> hints.
> 
> Feature bit definition:
> CPUID_Fn80000021_EAX [bit 20] - Indicates support for IC prefetch.
> 
> This feature is analogous to Intel's PREFETCHITI (CPUID.(EAX=7,ECX=1):EDX),
> though the CPUID bit definitions differ between AMD and Intel.
> 
> Expose the feature to KVM guests.
> 
> The feature is documented in Processor Programming Reference (PPR)
> for AMD Family 1Ah Model 02h, Revision C1 (Link below).
> 
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
> Signed-off-by: Babu Moger <babu.moger@xxxxxxx>
> ---
>  arch/x86/include/asm/cpufeatures.h | 1 +
>  arch/x86/kvm/cpuid.c               | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 6c2c152d8a67..7d7507b3eefd 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -457,6 +457,7 @@
>  #define X86_FEATURE_AUTOIBRS		(20*32+ 8) /* Automatic IBRS */
>  #define X86_FEATURE_NO_SMM_CTL_MSR	(20*32+ 9) /* SMM_CTL MSR is not present */
>  
> +#define X86_FEATURE_PREFETCHI		(20*32+20) /* Prefetch Data/Instruction to Cache Level */
>  #define X86_FEATURE_SBPB		(20*32+27) /* Selective Branch Prediction Barrier */
>  #define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */
>  #define X86_FEATURE_SRSO_NO		(20*32+29) /* CPU is not affected by SRSO */

Acked-by: Borislav Petkov (AMD) <bp@xxxxxxxxx>

-- 
Regards/Gruss,
    Boris.

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