Re: [PATCH v6 3/6] clk: spacemit: Add clock support for SpacemiT K1 SoC

[Yixun Lan]

On 14:37 Tue 08 Apr     , Alex Elder wrote:
> On 4/1/25 12:24 PM, Haylen Chu wrote:
> > The clock tree of K1 SoC contains three main types of clock hardware
> > (PLL/DDN/MIX) and has control registers split into several multifunction
> > devices: APBS (PLLs), MPMU, APBC and APMU.
> > 
> > All register operations are done through regmap to ensure atomiciy
> > between concurrent operations of clock driver and reset,
> > power-domain driver that will be introduced in the future.
> > 
> > Signed-off-by: Haylen Chu <heylenay@xxxxxxx>
> 
> I have a few more comments here but I think this is getting very
> close to ready.  You addressed pretty much everything I mentioned.
> 
> > ---
> >   drivers/clk/Kconfig               |    1 +
> >   drivers/clk/Makefile              |    1 +
> >   drivers/clk/spacemit/Kconfig      |   18 +
> >   drivers/clk/spacemit/Makefile     |    5 +
> >   drivers/clk/spacemit/apbc_clks    |  100 +++
> >   drivers/clk/spacemit/ccu-k1.c     | 1316 +++++++++++++++++++++++++++++
> >   drivers/clk/spacemit/ccu_common.h |   48 ++
> >   drivers/clk/spacemit/ccu_ddn.c    |   83 ++
> >   drivers/clk/spacemit/ccu_ddn.h    |   47 ++
> >   drivers/clk/spacemit/ccu_mix.c    |  268 ++++++
> >   drivers/clk/spacemit/ccu_mix.h    |  218 +++++
> >   drivers/clk/spacemit/ccu_pll.c    |  157 ++++
> >   drivers/clk/spacemit/ccu_pll.h    |   86 ++
> >   13 files changed, 2348 insertions(+)
> >   create mode 100644 drivers/clk/spacemit/Kconfig
> >   create mode 100644 drivers/clk/spacemit/Makefile
> >   create mode 100644 drivers/clk/spacemit/apbc_clks
> >   create mode 100644 drivers/clk/spacemit/ccu-k1.c
> >   create mode 100644 drivers/clk/spacemit/ccu_common.h
> >   create mode 100644 drivers/clk/spacemit/ccu_ddn.c
> >   create mode 100644 drivers/clk/spacemit/ccu_ddn.h
> >   create mode 100644 drivers/clk/spacemit/ccu_mix.c
> >   create mode 100644 drivers/clk/spacemit/ccu_mix.h
> >   create mode 100644 drivers/clk/spacemit/ccu_pll.c
> >   create mode 100644 drivers/clk/spacemit/ccu_pll.h
> > 
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index 713573b6c86c..19c1ed280fd7 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -517,6 +517,7 @@ source "drivers/clk/samsung/Kconfig"
> >   source "drivers/clk/sifive/Kconfig"
> >   source "drivers/clk/socfpga/Kconfig"
> >   source "drivers/clk/sophgo/Kconfig"
> > +source "drivers/clk/spacemit/Kconfig"
> >   source "drivers/clk/sprd/Kconfig"
> >   source "drivers/clk/starfive/Kconfig"
> >   source "drivers/clk/sunxi/Kconfig"
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index bf4bd45adc3a..42867cd37c33 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -145,6 +145,7 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG)	+= samsung/
> >   obj-$(CONFIG_CLK_SIFIVE)		+= sifive/
> >   obj-y					+= socfpga/
> >   obj-y					+= sophgo/
> > +obj-y					+= spacemit/
> >   obj-$(CONFIG_PLAT_SPEAR)		+= spear/
> >   obj-y					+= sprd/
> >   obj-$(CONFIG_ARCH_STI)			+= st/
> > diff --git a/drivers/clk/spacemit/Kconfig b/drivers/clk/spacemit/Kconfig
> > new file mode 100644
> > index 000000000000..4c4df845b3cb
> > --- /dev/null
> > +++ b/drivers/clk/spacemit/Kconfig
> > @@ -0,0 +1,18 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +
> > +config SPACEMIT_CCU
> > +	tristate "Clock support for SpacemiT SoCs"
> 
> I don't know the answer to this, but...  Should this be a Boolean
> rather than tristate?  Can a SpacemiT K1 SoC function without the
> clock driver built in to the kernel?
> 
I agree to make it a Boolean, we've already made pinctrl driver Boolean
and pinctrl depend on clk, besides, the SoC is unlikely functional
without clock built in as it's such critical..

> > +	depends on ARCH_SPACEMIT || COMPILE_TEST
> > +	select MFD_SYSCON
> > +	help
> > +	  Say Y to enable clock controller unit support for SpacemiT SoCs.
> > +
> > +if SPACEMIT_CCU
> > +
> > +config SPACEMIT_K1_CCU
> > +	tristate "Support for SpacemiT K1 SoC"
> 
> If you decide SPACEMIT_CCU needs to be Boolean, this one should
> be Boolean too.
> 
[...] 
> > +	CCU_PLL_RATE(1600000000UL, 0x0050cd61, 0x43eaaaab),
> > +	CCU_PLL_RATE(1800000000UL, 0x0050cd61, 0x4b000000),
> > +	CCU_PLL_RATE(2000000000UL, 0x0050dd62, 0x2aeaaaab),
> > +	CCU_PLL_RATE(2457600000UL, 0x0050dd64, 0x330ccccd),
> > +	CCU_PLL_RATE(3000000000UL, 0x0050dd66, 0x3fe00000),
> > +	CCU_PLL_RATE(3200000000UL, 0x0050dd67, 0x43eaaaab),
> > +};
> > +
> > +CCU_PLL_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR3, MPMU_POSR,
> > +	       POSR_PLL1_LOCK, CLK_SET_RATE_GATE);
> > +CCU_PLL_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR3, MPMU_POSR,
> > +	       POSR_PLL2_LOCK, CLK_SET_RATE_GATE);
> > +CCU_PLL_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR3, MPMU_POSR,
> > +	       POSR_PLL3_LOCK, CLK_SET_RATE_GATE);
> > +
> 
> I suspect Yixun would like you to have lines like the next one be
> 84 characters wide--slighly wider than the 80 column limit.
> 
> I'm not going to ask you to change it (but he might).
> 
Yes, I do prefer 100 cloumn.. please check more of this files

But anyway, I can bear with it if clk subsystem maintainer have enforced
80 column policy for the whole clk subsystem, to make consistent

-- 
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55