[PATCH v2 5/5] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device
From: Jie Gan
Date: Wed Apr 09 2025 - 21:35:11 EST
Add interrupts to enable byte-cntr function for TMC ETR devices.
Signed-off-by: Jie Gan <jie.gan@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index a904960359d7..b091e941aa21 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -2427,6 +2427,11 @@ ctcu@4001000 {
clocks = <&aoss_qmp>;
clock-names = "apb";
+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "etr0",
+ "etr1";
+
in-ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.34.1