Re: [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property

[Marc Zyngier]

On Thu, 10 Apr 2025 07:00:55 +0100,
Krzysztof Kozlowski <krzk@xxxxxxxxxx> wrote:
> 
> On 10/04/2025 01:36, Vijay Balakrishna wrote:
> > From: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
> > 
> > Some ARM Cortex CPUs like the A53, A57 and A72 have Error Detection And
> > Correction (EDAC) support on their L1 and L2 caches. This is implemented
> > in implementation defined registers, so usage of this functionality is
> > not safe in virtualized environments or when EL3 already uses these
> > registers. This patch adds a edac-enabled flag which can be explicitly
> > set when EDAC can be used.
> 
> Can't hypervisor tell you that?

No, it can't. This is not an architecture feature, and KVM will gladly
inject an UNDEF exception if the guest tries to use this.

Which is yet another reason why this whole exercise is futile.

	M.

-- 
Without deviation from the norm, progress is not possible.