Re: [PATCH v2 10/12] pinctrl: renesas: rzg2l: Add support for RZ/V2N SoC

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, 7 Apr 2025 at 21:16, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add pinctrl support for the Renesas RZ/V2N SoC by reusing the existing
> RZ/V2H(P) pin configuration data. The PFC block is nearly identical, with
> the only difference being the absence of `PCIE1_RSTOUTB` on RZ/V2N.
>
> To accommodate this, move the `PCIE1_RSTOUTB` entry to the end of the
> `rzv2h_dedicated_pins` array and set `.n_dedicated_pins` to
> `ARRAY_SIZE(rzv2h_dedicated_pins) - 1` in the RZ/V2N OF data.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Thanks for your patch!

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>

Suggestion for improvement below.

> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -2304,7 +2304,6 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
>         { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
>                                                     PIN_CFG_IEN | PIN_CFG_PUPD)) },
>         { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
> -       { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
>         { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
>                                                      PIN_CFG_IEN | PIN_CFG_PUPD)) },
>         { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
> @@ -2359,6 +2358,14 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
>         { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
>         { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
>         { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
> +
> +       /*
> +        * This pin is only available on the RZ/V2H(P) SoC and not on the RZ/V2N.
> +        * Since this array is shared with the RZ/V2N SoC, this entry should be placed
> +        * at the end. This ensures that on the RZ/V2N, we can set
> +        * `.n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins) - 1,`.
> +        */
> +       { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
>  };

Alternatively, you can replace the single array by a structure
containing two arrays, one for common pins, and a second
for V2H-only pins, like the common and automotive arrays in
e.g. drivers/pinctrl/renesas/pfc-r8a7791.c.  That would get rid of
the literal "- 1" (and the need for a comment ;-), and would protect
against future mistakes.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds