Re: [PATCH v4] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree
From: Geert Uytterhoeven
Date: Fri Apr 11 2025 - 05:22:21 EST
Hi Thomas,
On Mon, 24 Mar 2025 at 15:51, Thomas Bonnefille
<thomas.bonnefille@xxxxxxxxxxx> wrote:
> From: Clément Léger <clement.leger@xxxxxxxxxxx>
>
> The EB board (Expansion board) supports both RZ/N1D and RZ-N1S. Since this
> configuration targets only the RZ/N1D, it is named r9a06g032-rzn1d400-eb.
> It adds support for the 2 additional switch ports (port C and D) that are
> available on that board.
>
> Signed-off-by: Clément Léger <clement.leger@xxxxxxxxxxx>
> [Thomas: move the DTS to the Renesas directory, declare the PHY LEDs]
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@xxxxxxxxxxx>
> Reviewed-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> Tested-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
> ---
> This short series adds support for the RZ/N1 Expansion Board. This board
> is a carrier board on which a daughter board (either RZ/N1D or RZ/N1S)
> can be plugged. The device-tree that is added by this series enables the
> use to the 2 external switch ports that are present on this board.
> ---
> V4:
> - Drop trailing whitespaces
>
> V3:
> - Drop bindings commit as it was applied to master
> - Move Makefile modification to arch/arm/boot/dts/renesas/Makefile
> - Declare LEDs in PHY.
> - Use the driver default LED configuration as there was no reason to
> use a different one.
Thanks for the update!
> --- /dev/null
> +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
> @@ -0,0 +1,120 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the RZN1D-EB Board
> + *
> + * Copyright (C) 2023 Schneider-Electric
> + *
> + */
> +
> +#include "r9a06g032-rzn1d400-db.dts"
> +
> +/ {
> + model = "RZN1D-EB Board";
> + compatible = "renesas,rzn1d400-eb", "renesas,rzn1d400-db",
> + "renesas,r9a06g032";
> +};
> +
> +&mii_conv2 {
> + renesas,miic-input = <MIIC_SWITCH_PORTD>;
> + status = "okay";
> +};
> +
> +&mii_conv3 {
> + renesas,miic-input = <MIIC_SWITCH_PORTC>;
> + status = "okay";
> +};
> +
> +&pinctrl{
Missing space.
> + pins_eth1: pins-eth1 {
> + pinmux = <RZN1_PINMUX(12, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(13, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(14, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(15, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(16, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(17, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(18, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(19, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(20, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(21, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(22, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(23, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
> + drive-strength = <6>;
> + bias-disable;
> + };
> +
> + pins_eth2: pins-eth2 {
> + pinmux = <RZN1_PINMUX(24, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(25, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(26, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(27, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(28, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(29, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(30, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(31, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(32, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(33, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(34, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(35, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
> + drive-strength = <6>;
> + bias-disable;
> + };
> +};
> +
> +&switch {
> + pinctrl-names = "default";
(from v2) No need to specify pinctrl-names, as it is inherited from
r9a06g032-rzn1d400-db.dts.
> + pinctrl-0 = <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <&pins_eth4>,
> + <&pins_mdio1>;
> +
> + mdio {
> + /* CN15 and CN16 switches must be configured in MDIO2 mode */
> + switch0phy1: ethernet-phy@1 {
> + reg = <1>;
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + led@0 {
> + reg = <0>;
color = <LED_COLOR_ID_GREEN>;
> + };
> + led@1 {
> + reg = <1>;
color = <LED_COLOR_ID_ORANGE>;
> + };
The above should also have one of:
function = LED_FUNCTION_LAN;
function = LED_FUNCTION_SPEED_LAN;
I don't know the LED function mapping.
> + led@2 {
> + reg = <2>;
> + };
LED2/_INT is used as an interrupt pin, not as an LED.
> + };
> + };
> +
> + switch0phy10: ethernet-phy@10 {
Same comments for this one.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds