Re: [net-next PATCH v2 01/14] dt-bindings: net: Add Xilinx PCS

[Rob Herring]

On Mon, Apr 07, 2025 at 07:17:32PM -0400, Sean Anderson wrote:
> Add a binding for the Xilinx 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE
> IP. This device is a soft device typically used to adapt between GMII
> and SGMII or 1000BASE-X (possbilty in combination with a serdes).
> pcs-modes reflects the modes available with the as configured when the
> device is synthesized. Multiple modes may be specified if dynamic
> reconfiguration is supported.
> 
> One PCS may contain "shared logic in core" which can be connected to
> other PCSs with "shared logic in example design." This primarily refers
> to clocking resources, allowing a reference clock to be shared by a bank
> of PCSs. To support this, if #clock-cells is defined then the PCS will
> register itself as a clock provider for other PCSs.
> 
> Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxxx>
> ---
> 
> Changes in v2:
> - Change base compatible to just xlnx,pcs
> - Drop #clock-cells description
> - Move #clock-cells after compatible
> - Remove second example
> - Rename pcs-modes to xlnx,pcs-modes
> - Reword commit message
> 
>  .../devicetree/bindings/net/xilinx,pcs.yaml   | 115 ++++++++++++++++++
>  1 file changed, 115 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/xilinx,pcs.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/xilinx,pcs.yaml b/Documentation/devicetree/bindings/net/xilinx,pcs.yaml
> new file mode 100644
> index 000000000000..f9ec032127cf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/xilinx,pcs.yaml
> @@ -0,0 +1,115 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/xilinx,pcs.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP
> +
> +maintainers:
> +  - Sean Anderson <sean.anderson@xxxxxxxx>
> +
> +description:

Needs '>' modifier for paragraphs.

With that,

Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>

> +  This is a soft device which implements the PCS and (depending on
> +  configuration) PMA layers of an IEEE Ethernet PHY. On the MAC side, it
> +  implements GMII. It may have an attached SERDES (internal or external), or
> +  may directly use LVDS IO resources. Depending on the configuration, it may
> +  implement 1000BASE-X, SGMII, 2500BASE-X, or 2.5G SGMII.
> +
> +  This device has a notion of "shared logic" such as reset and clocking
> +  resources which must be shared between multiple PCSs using the same I/O
> +  banks. Each PCS can be configured to have the shared logic in the "core"
> +  (instantiated internally and made available to other PCSs) or in the "example
> +  design" (provided by another PCS). PCSs with shared logic in the core are
> +  reset controllers, and generally provide several resets for other PCSs in the
> +  same bank.