Re: [PATCH v2 1/9] clk: renesas: rzv2h-cpg: Add support for static mux clocks

[Geert Uytterhoeven]

On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add support for `CLK_TYPE_SMUX` to register static muxed clocks on the
> Renesas RZ/V2H(P) SoC. Extend `cpg_core_clk` to include parent names,
> mux flags, and a new `smuxed` struct. Update clock registration to
> handle static mux clocks.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v6.16.


> ---
>  drivers/clk/renesas/rzv2h-cpg.c | 21 +++++++++++++++++++++
>  drivers/clk/renesas/rzv2h-cpg.h | 32 ++++++++++++++++++++++++++++++++
>  2 files changed, 53 insertions(+)
>
> diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
> index b8bed0c1d918..4cda36d7f0a7 100644
> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> @@ -399,6 +399,24 @@ rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core,
>         return div->hw.clk;
>  }
>
> +static struct clk * __init
> +rzv2h_cpg_mux_clk_register(const struct cpg_core_clk *core,
> +                          struct rzv2h_cpg_priv *priv)
> +{
> +       struct smuxed mux = core->cfg.smux;
> +       const struct clk_hw *clk_hw;
> +
> +       clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,
> +                                         core->parent_names, core->num_parents,
> +                                         core->flag, priv->base + mux.offset,
> +                                         mux.shift, mux.width,
> +                                         core->mux_flags, &priv->rmw_lock);
> +       if (IS_ERR(clk_hw))
> +               return ERR_CAST(clk_hw);
> +
> +       return clk_hw->clk;
> +}
> +
>  static struct clk
>  *rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
>                                void *data)
> @@ -483,6 +501,9 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
>         case CLK_TYPE_DDIV:
>                 clk = rzv2h_cpg_ddiv_clk_register(core, priv);
>                 break;
> +       case CLK_TYPE_SMUX:
> +               clk = rzv2h_cpg_mux_clk_register(core, priv);
> +               break;
>         default:
>                 goto fail;
>         }
> diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
> index 59f72fbed133..03e602d70f69 100644
> --- a/drivers/clk/renesas/rzv2h-cpg.h
> +++ b/drivers/clk/renesas/rzv2h-cpg.h
> @@ -53,6 +53,26 @@ struct ddiv {
>                 .monbit = _monbit \
>         })
>
> +/**
> + * struct smuxed - Structure for static muxed clocks
> + *
> + * @offset: register offset
> + * @shift: position of the divider field
> + * @width: width of the divider field
> + */
> +struct smuxed {
> +       unsigned int offset:11;
> +       unsigned int shift:4;
> +       unsigned int width:4;
> +};
> +
> +#define SMUX_PACK(_offset, _shift, _width) \
> +       ((struct smuxed){ \
> +               .offset = (_offset), \
> +               .shift = (_shift), \
> +               .width = (_width), \
> +       })
> +
>  #define CPG_CDDIV0             (0x400)
>  #define CPG_CDDIV1             (0x404)
>  #define CPG_CDDIV3             (0x40C)
> @@ -96,8 +116,12 @@ struct cpg_core_clk {
>                 unsigned int conf;
>                 struct ddiv ddiv;
>                 struct pll pll;
> +               struct smuxed smux;
>         } cfg;
>         const struct clk_div_table *dtable;
> +       const char * const *parent_names;
> +       unsigned int num_parents;
> +       u8 mux_flags;
>         u32 flag;
>  };
>
> @@ -107,6 +131,7 @@ enum clk_types {
>         CLK_TYPE_FF,            /* Fixed Factor Clock */
>         CLK_TYPE_PLL,
>         CLK_TYPE_DDIV,          /* Dynamic Switching Divider */
> +       CLK_TYPE_SMUX,          /* Static Mux */
>  };
>
>  #define DEF_TYPE(_name, _id, _type...) \
> @@ -125,6 +150,13 @@ enum clk_types {
>                 .parent = _parent, \
>                 .dtable = _dtable, \
>                 .flag = CLK_DIVIDER_HIWORD_MASK)
> +#define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \
> +       DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \
> +                .cfg.smux = _smux_packed, \
> +                .parent_names = _parent_names, \
> +                .num_parents = ARRAY_SIZE(_parent_names), \
> +                .flag = CLK_SET_RATE_PARENT, \
> +                .mux_flags = CLK_MUX_HIWORD_MASK)
>
>  /**
>   * struct rzv2h_mod_clk - Module Clocks definitions
> --
> 2.49.0
>


--
Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds