Re: [PATCH v2 6/9] clk: renesas: rzv2h-cpg: Ignore monitoring CLK_MON bits for external clocks

[Lad, Prabhakar]

Hi Geert,

On Tue, Apr 15, 2025 at 4:01 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Mon, 7 Apr 2025 at 18:52, Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Ignore CLK_MON bits when turning on/off module clocks that use an external
> > clock source.
> >
> > Introduce the `DEF_MOD_EXTERNAL()` macro for defining module clocks that
> > may have an external clock source. Update `rzv2h_cpg_register_mod_clk()`
> > to update mon_index.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> > --- a/drivers/clk/renesas/rzv2h-cpg.c
> > +++ b/drivers/clk/renesas/rzv2h-cpg.c
> > @@ -569,6 +569,25 @@ static void rzv2h_mod_clock_mstop_disable(struct rzv2h_cpg_priv *priv,
> >         spin_unlock_irqrestore(&priv->rmw_lock, flags);
> >  }
> >
> > +static bool rzv2h_mod_clock_is_external(struct rzv2h_cpg_priv *priv,
> > +                                       u16 ext_clk_offset,
> > +                                       u8 ext_clk_bit,
> > +                                       u8 ext_cond)
> > +{
> > +       u32 value;
> > +
> > +       if (!ext_clk_offset)
> > +               return false;
> > +
> > +       value = readl(priv->base + ext_clk_offset) & BIT(ext_clk_bit);
>
> As ext_clk_offset is actually the offset of the Static Mux Control
> Registers (CPG_SSELm), this reads the current state of the mux.
> However, can't the state be changed at runtime (despite it being named
> a "static mux")?
>
Agreed based on the HW manual this can be changed at runtime. So this
check needs to be done in the rzv2h_mod_clock_is_enabled().

Cheers,
Prabhakar