RE: [PATCH v5 6/7] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe

[Hongxing Zhu]

> -----Original Message-----
> From: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> Sent: 2025年4月15日 15:21
> To: Hongxing Zhu <hongxing.zhu@xxxxxxx>
> Cc: Frank Li <frank.li@xxxxxxx>; l.stach@xxxxxxxxxxxxxx; lpieralisi@xxxxxxxxxx;
> kw@xxxxxxxxx; robh@xxxxxxxxxx; bhelgaas@xxxxxxxxxx;
> shawnguo@xxxxxxxxxx; s.hauer@xxxxxxxxxxxxxx; kernel@xxxxxxxxxxxxxx;
> festevam@xxxxxxxxx; linux-pci@xxxxxxxxxxxxxxx;
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; imx@xxxxxxxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx
> Subject: Re: [PATCH v5 6/7] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe
> 
> On Mon, Apr 14, 2025 at 03:16:46AM +0000, Hongxing Zhu wrote:
> > > -----Original Message-----
> > > From: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> > > Sent: 2025年4月13日 23:33
> > > To: Hongxing Zhu <hongxing.zhu@xxxxxxx>
> > > Cc: Frank Li <frank.li@xxxxxxx>; l.stach@xxxxxxxxxxxxxx;
> > > lpieralisi@xxxxxxxxxx; kw@xxxxxxxxx; robh@xxxxxxxxxx;
> > > bhelgaas@xxxxxxxxxx; shawnguo@xxxxxxxxxx; s.hauer@xxxxxxxxxxxxxx;
> > > kernel@xxxxxxxxxxxxxx; festevam@xxxxxxxxx;
> > > linux-pci@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx;
> > > imx@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx
> > > Subject: Re: [PATCH v5 6/7] PCI: imx6: Add PLL clock lock check for
> > > i.MX95 PCIe
> > >
> > > On Tue, Apr 08, 2025 at 10:59:29AM +0800, Richard Zhu wrote:
> > > > Add PLL clock lock check for i.MX95 PCIe.
> > > >
> > > > Signed-off-by: Richard Zhu <hongxing.zhu@xxxxxxx>
> > > > Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> > > > ---
> > > >  drivers/pci/controller/dwc/pci-imx6.c | 28
> > > > +++++++++++++++++++++++++--
> > > >  1 file changed, 26 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > > > b/drivers/pci/controller/dwc/pci-imx6.c
> > > > index 7dcc9d88740d..c1d128ec255d 100644
> > > > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > > > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > > > @@ -45,6 +45,9 @@
> > > >  #define IMX95_PCIE_PHY_GEN_CTRL			0x0
> > > >  #define IMX95_PCIE_REF_USE_PAD			BIT(17)
> > > >
> > > > +#define IMX95_PCIE_PHY_MPLLA_CTRL		0x10
> > > > +#define IMX95_PCIE_PHY_MPLL_STATE		BIT(30)
> > > > +
> > > >  #define IMX95_PCIE_SS_RW_REG_0			0xf0
> > > >  #define IMX95_PCIE_REF_CLKEN			BIT(23)
> > > >  #define IMX95_PCIE_PHY_CR_PARA_SEL		BIT(9)
> > > > @@ -479,6 +482,23 @@ static void
> > > imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie)
> > > >  		dev_err(dev, "PCIe PLL lock timeout\n");  }
> > > >
> > > > +static int imx95_pcie_wait_for_phy_pll_lock(struct imx_pcie
> > > > +*imx_pcie) {
> > > > +	u32 val;
> > > > +	struct device *dev = imx_pcie->pci->dev;
> > > > +
> > > > +	if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr,
> > > > +				     IMX95_PCIE_PHY_MPLLA_CTRL, val,
> > > > +				     val & IMX95_PCIE_PHY_MPLL_STATE,
> > > > +				     PHY_PLL_LOCK_WAIT_USLEEP_MAX,
> > > > +				     PHY_PLL_LOCK_WAIT_TIMEOUT)) {
> > > > +		dev_err(dev, "PCIe PLL lock timeout\n");
> > > > +		return -ETIMEDOUT;
> > > > +	}
> > > > +
> > > > +	return 0;
> > > > +}
> > > > +
> > > >  static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie)  {
> > > >  	unsigned long phy_rate = 0;
> > > > @@ -824,6 +844,8 @@ static int imx95_pcie_core_reset(struct
> > > > imx_pcie
> > > *imx_pcie, bool assert)
> > > >  		regmap_read_bypassed(imx_pcie->iomuxc_gpr,
> > > IMX95_PCIE_RST_CTRL,
> > > >  				     &val);
> > > >  		udelay(10);
> > > > +	} else {
> > > > +		return imx95_pcie_wait_for_phy_pll_lock(imx_pcie);
> > >
> > > Is this PLL lock related to COLD_RESET? It doesn't look like it. If
> > > unrelated, it should be called wherever required.
> > > imx95_pcie_core_reset() is supposed to only assert/deassert the
> COLD_RESET.
> > >
> > > If related, please explain how.
> > Thanks for your kindly review.
> > To make sure the HW state is correct to continue the sequential initializations.
> > The PLL lock or not check would be kicked off after the COLD_RESET is
> > de-asserted for i.MX95 PCIe.
> > So, the PLL lock check is added at the end of de-assertion in
> >  imx95_pcie_core_reset() function.
> >
> 
> But imx95_pcie_core_reset() is not doing anything for deassert other than
> waiting for PLL lock. Hence my question.
Okay, I see.
How about add one more callback (e.x wait_pll_lock) and do the pll lock
 check after imx_pcie_deassert_core_reset()?

Best Regards
Richard Zhu
> 
> - Mani
> 
> --
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