Re: [PATCH 4/4] perf/x86/amd/uncore: Prevent UMC counters from saturating

[Song Liu]

> On Apr 9, 2025, at 12:57 AM, Sandipan Das <sandipan.das@xxxxxxx> wrote:
> 
> Unlike L3 and DF counters, UMC counters (PERF_CTRs) set the Overflow bit
> (bit 48) and saturate on overflow. A subsequent pmu->read() of the event
> reports an incorrect accumulated count as there is no difference between
> the previous and the current values of the counter.
> 
> To avoid this, inspect the current counter value and proactively reset
> the corresponding PERF_CTR register on every pmu->read(). Combined with
> the periodic reads initiated by the hrtimer, the counters never get a
> chance saturate but the resolution reduces to 47 bits.
> 
> Fixes: 25e56847821f ("perf/x86/amd/uncore: Add memory controller support")
> Signed-off-by: Sandipan Das <sandipan.das@xxxxxxx>

Reviewed-by: Song Liu <song@xxxxxxxxxx>

Thanks for the fix!