On Wed, Apr 16, 2025 at 11:53:56AM GMT, Frank Wunderlich wrote:
From: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
Add support for type switch by pericfg register between USB3/PCIe.
Signed-off-by: Frank Wunderlich <frank-w@xxxxxxxxxxxxxxx>
---
.../devicetree/bindings/phy/mediatek,xsphy.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
index 3b5253659e6f..5033d77c1239 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,xsphy.yaml
@@ -151,6 +151,22 @@ patternProperties:
minimum: 1
maximum: 31
+ mediatek,syscon-type:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+ description:
+ A phandle to syscon used to access the register of type switch,
+ the field should always be 3 cells long.
+ items:
+ items:
Missing -, because you have one phandle.
+ - description:
+ The first cell represents a phandle to syscon
Don't repeat constraints in free form text. "Foo bar system controller"
or "Phandle to foo bar system controller"
+ - description:
+ The second cell represents the register offset
"Baz register offset"
+ - description:
+ The third cell represents the index of config segment
"Index of config segment", but what is index of config?
Best regards,
Krzysztof