Re: [PATCH v4 01/15] clk: renesas: rzv2h-cpg: Add support for DSI clocks

[Lad, Prabhakar]

Hi Fabrizio,

On Thu, May 1, 2025 at 11:38 AM Fabrizio Castro
<fabrizio.castro.jz@xxxxxxxxxxx> wrote:
>
> Hi Alok,
>
> Thanks for your email.
>
> > From: ALOK TIWARI <alok.a.tiwari@xxxxxxxxxx>
> > Sent: 01 May 2025 10:51
> > Subject: Re: [PATCH v4 01/15] clk: renesas: rzv2h-cpg: Add support for DSI clocks
> >
> >
> > On 01-05-2025 02:10, Prabhakar wrote:
> > > From: Lad Prabhakar<prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > >
> > > Add support for PLLDSI and PLLDSI divider clocks.
> > >
> > > Introduce the `renesas-rzv2h-dsi.h` header to centralize and share
> > > PLLDSI-related data structures, limits, and algorithms between the RZ/V2H
> > > CPG and DSI drivers.
> > >
> > > The DSI PLL is functionally similar to the CPG's PLLDSI, but has slightly
> > > different parameter limits and omits the programmable divider present in
> > > CPG. To ensure precise frequency calculations-especially for milliHz-level
> > > accuracy needed by the DSI driver-the shared algorithm allows both drivers
> > > to compute PLL parameters consistently using the same logic and input
> > > clock.
> > >
> > > Co-developed-by: Fabrizio Castro<fabrizio.castro.jz@xxxxxxxxxxx>
> > > Signed-off-by: Fabrizio Castro<fabrizio.castro.jz@xxxxxxxxxxx>
> > > Signed-off-by: Lad Prabhakar<prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> >
> > Acked-by: Alok Tiwari <alok.a.tiwari@xxxxxxxxxx>
>
> I am not sure it makes sense for you to Ack this patch?
> Please have a look at the process here:
> https://www.kernel.org/doc/Documentation/process/submitting-patches.rst
>
> Perhaps you meant to add your Reviewed-by tag instead?
>
I'm not sure a Reviewed-by tag would be appropriate either, as it
implies the reviewer has performed a thorough technical review of the
patch.

Cheers,
Prabhakar