[PATCH 2/5] arm64: dts: qcom: sc8280xp: Add PCIe IOMMU

[Nikita Travkin]

sc8280xp has an SMMUv3 connected to PCIe which is normally controlled by
QHEE and is thus transparent to the OS. However if we boot Linux in EL2,
without QHEE, we need to manage this IOMMU ourselves. To make that
easier, and since the hardware actually exists, just not "usually"
managed by Linux, describe it in the dts as "reserved".

Signed-off-by: Nikita Travkin <nikita@xxxxxxx>
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 35ef31d4ecf26125407bb64dd2de6e777a3400a3..27d21e1a2d50c6fc12f324ab2b4dfa4b99791b81 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4927,6 +4927,20 @@ rx-pins {
 			};
 		};
 
+		pcie_smmu: iommu@14f80000 {
+			compatible = "arm,smmu-v3";
+			reg = <0 0x14f80000 0 0x80000>;
+			#iommu-cells = <1>;
+			interrupts = <GIC_SPI 951 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 955 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 953 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eventq",
+					  "gerror",
+					  "cmdq-sync";
+			dma-coherent;
+			status = "reserved"; /* Controlled by QHEE. */
+		};
+
 		apps_smmu: iommu@15000000 {
 			compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
 			reg = <0 0x15000000 0 0x100000>;

-- 
2.49.0