Re: [PATCH v2 09/29] dt-bindings: clock: mediatek: Describe MT8196 peripheral clock controllers

[AngeloGioacchino Del Regno]

Il 24/06/25 18:02, Krzysztof Kozlowski ha scritto:
> On 24/06/2025 16:32, Laura Nao wrote:
> > +  '#reset-cells':
> > +    const: 1
> > +    description:
> > +      Reset lines for PEXTP0/1 and UFS blocks.
> > +
> > +  mediatek,hardware-voter:
> > +    $ref: /schemas/types.yaml#/definitions/phandle
> > +    description:
> > +      On the MT8196 SoC, a Hardware Voter (HWV) backed by a fixed-function
> > +      MCU manages clock and power domain control across the AP and other
> > +      remote processors. By aggregating their votes, it ensures clocks are
> > +      safely enabled/disabled and power domains are active before register
> > +      access.
>
> Resource voting is not via any phandle, but either interconnects or
> required opps for power domain.

Sorry, I'm not sure who is actually misunderstanding what, here... let me try to
explain the situation:

This is effectively used as a syscon - as in, the clock controllers need to perform
MMIO R/W on both the clock controller itself *and* has to place a vote to the clock
controller specific HWV register.

This is done for MUX-GATE and GATE clocks, other than for power domains.

Note that the HWV system is inside of the power domains controller, and it's split
on a per hardware macro-block basis (as per usual MediaTek hardware layout...).

The HWV, therefore, does *not* vote for clock *rates* (so, modeling OPPs would be
a software quirk, I think?), does *not* manage bandwidth (and interconnect is for
voting BW only?), and is just a "switch to flip".

Is this happening because the description has to be improved and creating some
misunderstanding, or is it because we are underestimating and/or ignoring something
here?

Cheers,
Angelo

> I already commented on this, so don't send v3 with the same.
>
> Best regards,
> Krzysztof