Re: [PATCH v4 1/4] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs

[Geert Uytterhoeven]

On Wed, 2 Jul 2025 at 02:57, John Madieu <john.madieu.xa@xxxxxxxxxxxxxx> wrote:
> Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH 0-1)
> IPs found on the RZ/G3E SoC. This includes various PLLs, dividers, and mux
> clocks needed by these two GBETH IPs.
>
> Reviewed-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Signed-off-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>

> v4:
>  - Renames clock names to match V2Hs
>  - Uses DEF_MOD_MUX_EXTERNAL instead of DEF_MOD for Tx and Rx clks
>  - Drops Tested-by tag from Biju

Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v6.17.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds