Re: [PATCH -v4] ufs: ufs-qcom: Align programming sequence of Shared ICE for UFS controller v5

[Palash Kambar]

On 8/14/2025 2:40 PM, Konrad Dybcio wrote:
> On 8/14/25 8:58 AM, Palash Kambar wrote:
>> Disabling the AES core in Shared ICE is not supported during power
>> collapse for UFS Host Controller v5.0, which may lead to data errors
>> after Hibern8 exit. To comply with hardware programming guidelines
>> and avoid this issue, issue a sync reset to ICE upon power collapse
>> exit.
>>
>> Hence follow below steps to reset the ICE upon exiting power collapse
>> and align with Hw programming guide.
>>
>> a. Assert the ICE sync reset by setting both SYNC_RST_SEL and
>>    SYNC_RST_SW bits in UFS_MEM_ICE_CFG
>> b. Deassert the reset by clearing SYNC_RST_SW in  UFS_MEM_ICE_CFG
>>
>> Signed-off-by: Palash Kambar <quic_pkambar@xxxxxxxxxxx>
>>
>> ---
>> changes from V1:
>> 1) Incorporated feedback from Konrad and Manivannan by adding a delay
>>    between ICE reset assertion and deassertion.
>> 2) Removed magic numbers and replaced them with meaningful constants.
>>
>> changes from V2:
>> 1) Addressed Manivannan's comment and moved change to ufs_qcom_resume.
>>
>> changes from V3:
>> 1) Addressed Manivannan's comments and added bit field values and
>>    updated patch description.
>> ---
>>  drivers/ufs/host/ufs-qcom.c | 19 +++++++++++++++++++
>>  drivers/ufs/host/ufs-qcom.h |  2 +-
>>  2 files changed, 20 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
>> index 444a09265ded..9195a5c695a5 100644
>> --- a/drivers/ufs/host/ufs-qcom.c
>> +++ b/drivers/ufs/host/ufs-qcom.c
>> @@ -38,6 +38,9 @@
>>  #define DEEMPHASIS_3_5_dB	0x04
>>  #define NO_DEEMPHASIS		0x0
>>  
>> +#define UFS_ICE_SYNC_RST_SEL	BIT(3)
>> +#define UFS_ICE_SYNC_RST_SW	BIT(4)
>> +
>>  enum {
>>  	TSTBUS_UAWM,
>>  	TSTBUS_UARM,
>> @@ -756,6 +759,22 @@ static int ufs_qcom_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
>>  	if (err)
>>  		return err;
>>  
>> +	if ((!ufs_qcom_is_link_active(hba)) &&
>> +	    host->hw_ver.major == 5 &&
>> +	    host->hw_ver.minor == 0 &&
>> +	    host->hw_ver.step == 0) {
>> +		ufshcd_writel(hba, UFS_ICE_SYNC_RST_SEL | UFS_ICE_SYNC_RST_SW, UFS_MEM_ICE_CFG);
>> +		ufshcd_readl(hba, UFS_MEM_ICE_CFG);
>> +		/*
>> +		 * HW documentation doesn't recommend any delay between the
>> +		 * reset set and clear. But we are enforcing an arbitrary delay
>> +		 * to give flops enough time to settle in.
>> +		 */
>> +		usleep_range(50, 100);
>> +		ufshcd_writel(hba, UFS_ICE_SYNC_RST_SEL, UFS_MEM_ICE_CFG);
> 
> This was supposed to be '0', IIRC

Thanks for catching the error Konrad, will update.

-Palash K