[Patch v3 0/7] x86 perf bug fixes and optimization

From: Dapeng Mi
Date: Tue Aug 19 2025 - 22:32:08 EST


Changes:
v2 -> v3:
* Rebase to latest tip perf/core tree.
* Rewrite commit message to explain why NULL access happens and
refine code (Patch 3/7)
* Refine commit message of patch 6/7
* Dump counters bitmap instead of absolute counter in boot message
(patch 7/7)

v1 -> v2:
* Rebase to 6.17-rc1.
* No code changes.

Tests:
* Run perf stats/record commands on Intel Sapphire Rapids platform, no
issue is found.

History:
v2: https://lore.kernel.org/all/20250811090034.51249-1-dapeng1.mi@xxxxxxxxxxxxxxx/
v1:
* Patch 1/6: https://lore.kernel.org/all/20250606111606.84350-1-dapeng1.mi@xxxxxxxxxxxxxxx/
* Patch 2/6: https://lore.kernel.org/all/20250529080236.2552247-1-dapeng1.mi@xxxxxxxxxxxxxxx/
* Patch 3/6: https://lore.kernel.org/all/20250718062602.21444-1-dapeng1.mi@xxxxxxxxxxxxxxx/
* Patches 4-6/6: https://lore.kernel.org/all/20250717090302.11316-1-dapeng1.mi@xxxxxxxxxxxxxxx/

Dapeng Mi (7):
perf/x86/intel: Use early_initcall() to hook bts_init()
perf/x86/intel: Fix IA32_PMC_x_CFG_B MSRs access error
perf/x86: Check if cpuc->events[*] pointer exists before accessing it
perf/x86: Add PERF_CAP_PEBS_TIMING_INFO flag
perf/x86/intel: Change macro GLOBAL_CTRL_EN_PERF_METRICS to
BIT_ULL(48)
perf/x86/intel: Add ICL_FIXED_0_ADAPTIVE bit into
INTEL_FIXED_BITS_MASK
perf/x86: Print PMU counters bitmap in x86_pmu_show_pmu_cap()

arch/x86/events/core.c | 16 +++++++++-------
arch/x86/events/intel/bts.c | 2 +-
arch/x86/events/intel/core.c | 21 +++++++++------------
arch/x86/events/intel/ds.c | 10 ++++++++++
arch/x86/include/asm/msr-index.h | 14 ++++++++------
arch/x86/include/asm/perf_event.h | 8 ++++++--
arch/x86/kvm/pmu.h | 2 +-
tools/arch/x86/include/asm/msr-index.h | 14 ++++++++------
8 files changed, 52 insertions(+), 35 deletions(-)


base-commit: 448f97fba9013ffa13f5dd82febd18836b189499
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2.34.1