Re: [PATCH v9 07/18] x86/apic: Add support to send IPI for Secure AVIC

[Borislav Petkov]

On Mon, Aug 11, 2025 at 03:14:33PM +0530, Neeraj Upadhyay wrote:
> With Secure AVIC only Self-IPI is accelerated. To handle all the
> other IPIs, add new callbacks for sending IPI. These callbacks write
> to the IRR of the target guest vCPU's APIC backing page and issue
> GHCB protocol MSR write event for the hypervisor to notify the
> target vCPU about the new interrupt request.
> 
> For Secure AVIC GHCB APIC MSR writes, reuse GHCB msr handling code in
	     ^^^^^^^^^^^^^^^^^^

say what now?!

> +void savic_ghcb_msr_write(u32 reg, u64 value)

I guess this belongs into x2apic_savic.c.

> +{
> +	u64 msr = APIC_BASE_MSR + (reg >> 4);
> +	struct pt_regs regs = {
> +		.cx = msr,
> +		.ax = lower_32_bits(value),
> +		.dx = upper_32_bits(value)
> +	};
> +	struct es_em_ctxt ctxt = { .regs = &regs };
> +	struct ghcb_state state;
> +	enum es_result res;
> +	struct ghcb *ghcb;
> +
> +	guard(irqsave)();
> +
> +	ghcb = __sev_get_ghcb(&state);
> +	vc_ghcb_invalidate(ghcb);
> +
> +	res = sev_es_ghcb_handle_msr(ghcb, &ctxt, true);
> +	if (res != ES_OK) {
> +		pr_err("Secure AVIC msr (0x%llx) write returned error (%d)\n", msr, res);
> +		/* MSR writes should never fail. Any failure is fatal error for SNP guest */
> +		snp_abort();
> +	}
> +
> +	__sev_put_ghcb(&state);
> +}

...

> +static inline void self_ipi_reg_write(unsigned int vector)
> +{
> +	/*
> +	 * Secure AVIC hardware accelerates guest's MSR write to SELF_IPI
> +	 * register. It updates the IRR in the APIC backing page, evaluates
> +	 * the new IRR for interrupt injection and continues with guest
> +	 * code execution.
> +	 */

Why is that comment here? It is above a WRMSR write. What acceleration is it
talking about?

> +	native_apic_msr_write(APIC_SELF_IPI, vector);
> +}

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette