Re: [PATCH] x86: add hintable NOPs emulation
From: Marcos Del Sol Vives
Date: Thu Aug 21 2025 - 15:46:58 EST
El 21/08/2025 a las 20:40, David Laight escribió:
> On Thu, 21 Aug 2025 14:46:59 +0200
> Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
>> It would mean cloning the page as private. Yes you can do it, uprobes
>> has all the code for this. But it has non-trivial memory overhead.
>
> I was thinking it would be safe to do this change without cloning the page.
> After all the change is needed for all processes executing the code.
> That might only be easy on UP systems - but I doubt the affected CPU are SMP.
>
> David
>
Actually...
marcos@vdx3:~$ nproc
2
marcos@vdx3:~$ cat /proc/cpuinfo
processor : 0
vendor_id : Vortex86 SoC
cpu family : 6
model : 1
model name : Vortex86DX3
stepping : 1
cpu MHz : 1000.017
physical id : 0
siblings : 1
core id : 0
cpu cores : 1
apicid : 0
initial apicid : 0
fdiv_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 3
wp : yes
flags : fpu pse tsc msr cx8 apic sep pge cmov mmx fxsr sse cpuid
bugs : itlb_multihit
bogomips : 2000.03
clflush size : 32
cache_alignment : 32
address sizes : 32 bits physical, 32 bits virtual
power management:
processor : 1
vendor_id : Vortex86 SoC
cpu family : 6
model : 1
model name : Vortex86DX3
stepping : 1
cpu MHz : 1000.017
physical id : 1
siblings : 1
core id : 0
cpu cores : 1
apicid : 1
initial apicid : 1
fdiv_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 3
wp : yes
flags : fpu pse tsc msr cx8 apic sep pge cmov mmx fxsr sse cpuid
bugs : itlb_multihit
bogomips : 2000.03
clflush size : 32
cache_alignment : 32
address sizes : 32 bits physical, 32 bits virtual
power management:
Vortex SoCs are true oddballs, aren't they?