Re: [PATCH net-next v2 6/9] net: pcs: rzn1-miic: Make switch mode mask SoC-specific

[Lad, Prabhakar]

Hi Andrew and Geert,

Thank you for the review.

On Thu, Sep 4, 2025 at 9:37 PM Andrew Lunn <andrew@xxxxxxx> wrote:
>
> On Thu, Sep 04, 2025 at 12:42:00PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Move the hardcoded switch mode mask definition into the SoC-specific
> > miic_of_data structure. This allows each SoC to define its own mask
> > value rather than relying on a single fixed constant. For RZ/N1 the
> > mask remains GENMASK(4, 0).
> >
> > This is in preparation for adding support for RZ/T2H, where the
> > switch mode mask is GENMASK(2, 0).
>
> > -#define MIIC_MODCTRL_SW_MODE         GENMASK(4, 0)
>
> >       miic_reg_writel(miic, MIIC_MODCTRL,
> > -                     FIELD_PREP(MIIC_MODCTRL_SW_MODE, cfg_mode));
> > +                     ((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
>
> _ffs() should return 0 for both GENMASK(2,0) and GENMASK(4, 0). So
> this __ffs() is pointless.
>
Agreed.

> You might however want to add a comment that this assumption is being
> made.
>
I will add the below comment for this, so that once Geert's series [0]
hits in it can be easily searched and replaced.

/*
* TODO: Replace with FIELD_PREP() when compile-time
* constant restriction is lifted. Currently __ffs() returns 0 for sw_mode_mask.
*/

[0] https://lore.kernel.org/all/cover.1739540679.git.geert+renesas@xxxxxxxxx

Cheers,
Prabhakar