Re: [PATCH v2 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
From: Jyothi Kumar Seerapu
Date: Wed Oct 15 2025 - 06:47:42 EST
On 9/26/2025 2:46 AM, Dmitry Baryshkov wrote:
On Thu, Sep 25, 2025 at 11:58:10AM +0530, Pankaj Patil wrote:Hi Dmitry, will add aliases for the necessary ones and remove the rest.>
From: Jyothi Kumar Seerapu <jyothi.seerapu@xxxxxxxxxxxxxxxx>
Add device tree support for QUPv3 serial engine protocols on Glymur.
Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
support of GPI DMA engines.
Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@xxxxxxxxxxxxxxxx>
Signed-off-by: Pankaj Patil <pankaj.patil@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 43 +
arch/arm64/boot/dts/qcom/glymur.dtsi | 3041 +++++++++++++++++++++++++++++--
2 files changed, 2936 insertions(+), 148 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index a1714ec8492961b211ec761f16b39245007533b8..4561c0b87b017cba0a1db8814123a070b37fd434 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -13,6 +13,49 @@ / {
aliases {
serial0 = &uart21;
+ serial1 = &uart14;
+ i2c0 = &i2c16;
+ i2c1 = &i2c17;
+ i2c2 = &i2c18;
+ i2c3 = &i2c19;
+ i2c4 = &i2c20;
+ i2c5 = &i2c22;
+ i2c6 = &i2c23;
+ i2c7 = &i2c8;
+ i2c8 = &i2c9;
+ i2c9 = &i2c10;
+ i2c10 = &i2c11;
+ i2c11 = &i2c12;
+ i2c12 = &i2c13;
+ i2c13 = &i2c15;
+ i2c14 = &i2c0;
+ i2c15 = &i2c1;
+ i2c16 = &i2c2;
+ i2c17 = &i2c3;
+ i2c18 = &i2c4;
+ i2c19 = &i2c5;
+ i2c20 = &i2c6;
+ spi0 = &spi16;
+ spi1 = &spi17;
+ spi2 = &spi18;
+ spi3 = &spi19;
+ spi4 = &spi20;
+ spi5 = &spi22;
+ spi6 = &spi23;
+ spi7 = &spi8;
+ spi8 = &spi9;
+ spi9 = &spi10;
+ spi10 = &spi11;
+ spi11 = &spi12;
+ spi12 = &spi13;
+ spi13 = &spi15;
+ spi14 = &spi0;
+ spi15 = &spi1;
+ spi16 = &spi2;
+ spi17 = &spi3;
+ spi18 = &spi4;
+ spi19 = &spi5;
+ spi20 = &spi6;
This is a very weird numbering. Could you please add a comment,
explaining it?
};
chosen {