Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
From: Jyothi Kumar Seerapu
Date: Wed Oct 15 2025 - 06:54:06 EST
On 10/11/2025 4:46 PM, Abel Vesa wrote:
On 25-09-25 12:02:12, Pankaj Patil wrote:
From: Jyothi Kumar Seerapu <jyothi.seerapu@xxxxxxxxxxxxxxxx>
Add device tree support for QUPv3 serial engine protocols on Glymur.
Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
support of GPI DMA engines.
Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@xxxxxxxxxxxxxxxx>
Signed-off-by: Pankaj Patil <pankaj.patil@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 43 +
arch/arm64/boot/dts/qcom/glymur.dtsi | 3041 +++++++++++++++++++++++++++++--
2 files changed, 2936 insertions(+), 148 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index f1c5a0cb483670e9f8044e250950693b4a015479..8674465b22707207523caa8ad635d95a3396497a 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
[...]
+ qup_i2c22_data_clk: qup-i2c22-data-clk-state {
+ sda_pins {
+ /* SDA */
+ pins = "gpio88";
+ function = "qup2_se6";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+
+ scl-pins {
+ /* SCL */
+ pins = "gpio89";
+ function = "qup2_se6";
+ drive-strength = <2>;
+ bias-pull-up = <2200>;
+ };
+ };
Re-write all of these like the following:
qup_i2c22_data_clk: qup-i2c22-data-clk-state {
/* SDA, SCL */
pins = "gpio88", "gpio89";
function = "qup2_se6";
drive-strength = <2>;
bias-pull-up = <2200>;
};
Just like we did on X1E80100.
Sure, that makes sense, as the same properties apply to both the SCL and SDA pins.