Re: [PATCH] clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src

[Quentin Schulz]

Hi Heiko,

On 10/8/25 3:31 PM, Heiko Stuebner wrote:
> dclk_vop2_src currently has CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
> flags set, which is vastly different than dclk_vop0_src or dclk_vop1_src,
> which have none of those.
>
> With these flags in dclk_vop2_src, actually setting the clock then results
> in a lot of other peripherals breaking, because setting the rate results
> in the PLL source getting changed:
>
> [   14.898718] clk_core_set_rate_nolock: setting rate for dclk_vop2 to 152840000
> [   15.155017] clk_change_rate: setting rate for pll_gpll to 1680000000
> [ clk adjusting every gpll user ]
>
> This includes possibly the other vops, i2s, spdif and even the uarts.
> Among other possible things, this breaks the uart console on a board
> I use. Sometimes it recovers later on, but there will be a big block

I can reproduce on the same board as yours and this fixes the issue 
indeed (note I can only reproduce for now when display the modetest 
pattern, otherwise after boot the console seems fine to me).

So,

Reviewed-by: Quentin Schulz <quentin.schulz@xxxxxxxxx>
Tested-by: Quentin Schulz <quentin.schulz@xxxxxxxxx> # RK3588 Tiger w/ 
DP carrierboard

> of garbled output for a while at least.
>
> Shared PLLs should not be changed by individual users, so drop these
> flags from dclk_vop2_src and make the flags the same as on dclk_vop0
> and dclk_vop1.

I hope there isn't a hardware reason for CLK_SET_RATE_NO_REPARENT which 
we remove here. But there's only one consumer of this clock (dclk_vop2) 
so this would be an isolated problem if there ever is one and now we 
match vop0 and vop1 behavior and I like consistency :)

Thanks!
Quentin