Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines
From: Jyothi Kumar Seerapu
Date: Wed Oct 15 2025 - 10:12:28 EST
On 10/15/2025 7:03 PM, Dmitry Baryshkov wrote:
On Wed, Oct 15, 2025 at 03:58:31PM +0530, Jyothi Kumar Seerapu wrote:In other platforms, the status is set to 'disabled' in the SoC device tree file and enabled in the board-specific device tree files.
On 9/25/2025 3:48 PM, Konrad Dybcio wrote:
On 9/25/25 8:32 AM, Pankaj Patil wrote:
From: Jyothi Kumar Seerapu <jyothi.seerapu@xxxxxxxxxxxxxxxx>
Add device tree support for QUPv3 serial engine protocols on Glymur.
Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
support of GPI DMA engines.
Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@xxxxxxxxxxxxxxxx>
Signed-off-by: Pankaj Patil <pankaj.patil@xxxxxxxxxxxxxxxx>
---
[...]
+ gpi_dma2: dma-controller@800000 {
+ compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0 0x00800000 0 0x60000>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <16>;
+ dma-channel-mask = <0x3f>;
+ #dma-cells = <3>;
+ iommus = <&apps_smmu 0xd76 0x0>;
+ status = "ok";
this is implied by default, drop
Hi Konard,
Do you mean we should remove the status property for all QUPs and GPI_DMAs
from the common device tree (SOC) and enable them only in the board-specific
device tree files?
Could you please check how it is done for all other platforms?
I believe it's fine to make the same change here.