Re: [PATCH 03/15] arm64: dts: allwinner: h616: add NAND controller

[Richard GENOUD]

Le 11/10/2025 à 12:33, Jernej Škrabec a écrit :
> Dne petek, 10. oktober 2025 ob 10:40:30 Srednjeevropski poletni čas je Richard Genoud napisal(a):
> > The H616 has a NAND controller quite similar to the A10/A23 ones, but
> > with some register differences, more clocks (for ECC and MBUS), more ECC
> > strengths, so this requires a new compatible string.
> >
> > This patch adds the NAND controller node and pins in the device tree.
> >
> > Signed-off-by: Richard Genoud <richard.genoud@xxxxxxxxxxx>
> > ---
> >   .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 50 +++++++++++++++++++
> >   1 file changed, 50 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> > index ceedae9e399b..60626eba7f7c 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> > @@ -278,6 +278,37 @@ ir_rx_pin: ir-rx-pin {
> >   				function = "ir_rx";
> >   			};
> >   
> > +			nand_pins: nand-pins {
> > +				pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9",
> > +				       "PC10", "PC11", "PC12", "PC13", "PC14",
> > +				       "PC15", "PC16";
> > +				function = "nand0";
> > +			};
> > +
> > +			nand_cs0_pin: nand-cs0-pin {
> > +				pins = "PC4";
> > +				function = "nand0";
> > +				bias-pull-up;
> > +			};
> > +
> > +			nand_cs1_pin: nand-cs1-pin {
> > +				pins = "PC3";
> > +				function = "nand0";
> > +				bias-pull-up;
> > +			};
> > +
> > +			nand_rb0_pin: nand-rb0-pin {
> > +				pins = "PC6";
> > +				function = "nand0";
> > +				bias-pull-up;
> > +			};
> > +
> > +			nand_rb1_pin: nand-rb1-pin {
> > +				pins = "PC7";
> > +				function = "nand0";
> > +				bias-pull-up;
> > +			};
> > +
> >   			mmc0_pins: mmc0-pins {
> >   				pins = "PF0", "PF1", "PF2", "PF3",
> >   				       "PF4", "PF5";
> > @@ -440,6 +471,25 @@ mmc2: mmc@4022000 {
> >   			#size-cells = <0>;
> >   		};
> >   
> > +		nfc: nand-controller@4011000 {
>
> Nodes are sorted by memory address. So this one should be moved before
> mmc2 and possibly others.
Indeed.
I'll fix that.

> > +			compatible = "allwinner,sun50i-h616-nand-controller";
> > +			reg = <0x04011000 0x1000>;
> > +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND0>,
> > +				<&ccu CLK_NAND1>, <&ccu CLK_MBUS_NAND>;
> > +			clock-names = "ahb", "mod", "ecc", "mbus";
> > +			resets = <&ccu RST_BUS_NAND>;
> > +			reset-names = "ahb";
> > +			dmas = <&dma 10>;
> > +			dma-names = "rxtx";
> > +			pinctrl-names = "default";
> > +			pinctrl-0 = <&nand_pins>, <&nand_cs0_pin>,
> > +				<&nand_cs1_pin>, <&nand_rb0_pin>,
> > +				<&nand_rb1_pin>;
>
> Are you sure that each nand device will use exactly this pin configuration?
> IIUC, not all chips will have two CS and two RB pins. If so, pinctrl nodes
> should be moved to device DT and pins subnodes should be marked with
> /omit-if-no-ref/.

You're right, all pins may not be used.

Thanks!

> Best regards,
> Jernej
>
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +		};
> > +
> >   		uart0: serial@5000000 {
> >   			compatible = "snps,dw-apb-uart";
> >   			reg = <0x05000000 0x400>;

--
Richard Genoud, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com