Re: [PATCH 1/2] i2c: tegra: Add logic to support different register offsets
From: Jon Hunter
Date: Fri Oct 24 2025 - 11:13:47 EST
On 01/10/2025 16:36, Kartik Rajput wrote:
Tegra410 use different offsets for existing I2C registers, update
the logic to use appropriate offsets per SoC.
Signed-off-by: Kartik Rajput <kkartik@xxxxxxxxxx>
---
drivers/i2c/busses/i2c-tegra.c | 499 ++++++++++++++++++++++-----------
1 file changed, 334 insertions(+), 165 deletions(-)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 038809264526..1e26d67cbd30 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
...
+static const struct tegra_i2c_regs tegra20_i2c_regs_vi = {
+ .cnfg = 0x0c00 + (0x000 << 2),
+ .status = 0x0c00 + (0x01c << 2),
+ .sl_cnfg = 0x0c00 + (0x020 << 2),
+ .sl_addr1 = 0x0c00 + (0x02c << 2),
+ .sl_addr2 = 0x0c00 + (0x030 << 2),
+ .tlow_sext = 0x0c00 + (0x034 << 2),
+ .tx_fifo = 0x0c00 + (0x050 << 2),
+ .rx_fifo = 0x0c00 + (0x054 << 2),
+ .packet_transfer_status = 0x0c00 + (0x058 << 2),
+ .fifo_control = 0x0c00 + (0x05c << 2),
+ .fifo_status = 0x0c00 + (0x060 << 2),
+ .int_mask = 0x0c00 + (0x064 << 2),
+ .int_status = 0x0c00 + (0x068 << 2),
+ .clk_divisor = 0x0c00 + (0x06c << 2),
+ .bus_clear_cnfg = 0x0c00 + (0x084 << 2),
+ .bus_clear_status = 0x0c00 + (0x088 << 2),
+ .config_load = 0x0c00 + (0x08c << 2),
+ .clken_override = 0x0c00 + (0x090 << 2),
+ .interface_timing_0 = 0x0c00 + (0x094 << 2),
+ .interface_timing_1 = 0x0c00 + (0x098 << 2),
+ .hs_interface_timing_0 = 0x0c00 + (0x09c << 2),
+ .hs_interface_timing_1 = 0x0c00 + (0x0a0 << 2),
+ .master_reset_cntrl = 0x0c00 + (0x0a8 << 2),
+ .mst_fifo_control = 0x0c00 + (0x0b4 << 2),
+ .mst_fifo_status = 0x0c00 + (0x0b8 << 2),
+ .sw_mutex = 0x0c00 + (0x0ec << 2),
Why do we define all the above with '<< 2'? Seems odd.
Jon
--
nvpublic