RE: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device tree

[Ryan Chen]

> Subject: Re: [PATCH v6 4/6] arm64: dts: aspeed: Add initial AST2700 SoC device
> tree
> 
> > > >> This probably needs some explanation: why are there two 'soc@...'
> > > >> devices? Is this literally two chips in the system, or are you
> > > >> describing two buses inside of the same SoC?
> > > >
> > > > The AST2700 is two soc connection with a property bus.
> > > > Sharing some decode registers. Each have it own ahb bus.
> > >
> > > I don't understand your explanation,
> >
> > Let me clarify more clearly:
> > The AST2700 is a dual-SoC architecture, consisting of two
> > interconnected SoCs, referred to as SoC0 and SoC1. Each SoC has its own
> clock/reset domains.
> > They are connected through an internal "property bus", which is
> > Aspeed's internal interconnect providing shared address decoding and
> > communication between the two SoCs.
> 
> By SoC are you just referring to peripherals? Or are there two sets of CPUs as
> well?
> 
> If it is just peripherals, this has been done before by Marvell.
> 
> See armada-cp11x.dtsi. Marvell calls it a CP, they are identical, so there is one
> description of it, which then gets included twice.
> 
Hi Andrew,

Thanks for asking - yes, the AST2700 is indeed a dual-SoC device, not just a split peripheral domain.

SoC0, referred to as the CPU die, contains a dual-core Cortex-A35 cluster and two Cortex-M4 cores, along with its own clock/reset domains and high-speed peripheral set.
SoC1, referred to as the I/O die, contains the Boot MCU and its own clock/reset domains and low-speed peripheral set, and is responsible for system boot and control functions.

The two SoCs are interconnected through Aspeed's internal "property bus", which provides shared address decoding and inter-SoC communication between the CPU and I/O dies.

This makes the AST2700 closer to a dual-die / dual-SoC configuration, rather than the Marvell CP model you mentioned, which only duplicates peripheral blocks under a single CPU domain.

I'll add this clarification in the commit message and DTS comments in the next revision to make the relationship between the two SoCs explicit.

Best regards,
Ryan